Patents by Inventor David Charles McClure

David Charles McClure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10306854
    Abstract: The present invention is in the field of soybean variety CW1410054 breeding and development. The present invention particularly relates to the soybean variety CW1410054 and its seed, cells, germplasm, plant parts, and progeny, and methods of using CW1410054 in a breeding program.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: June 4, 2019
    Assignee: Syngenta Participations AG
    Inventors: David Scott Lee, Jacob Charles Delheimer, Donald Bruce McClure
  • Patent number: 7411433
    Abstract: A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC power systems. The reset ramp control structure provides operational protection during fast ramp down conditions when standard reset circuitry may not be operational.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: August 12, 2008
    Assignee: STMicroelectronics, Inc.
    Inventors: David Charles McClure, Rong Yin
  • Patent number: 7368947
    Abstract: A voltage translating control structure for switching logic is described. A battery drain problem is corrected by this structure. The voltage translating feature allows reliable switching between power supply and battery even if the power supply voltage has significantly decreased. Operation is adaptable to include all DC power systems. Logic circuitry that also allows voltage translation is presented.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: May 6, 2008
    Assignee: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Patent number: 7333310
    Abstract: A bonding pad arrangement for an integrated circuit includes a bonding pad fabricated on a bonding area to enable bonding. A first ESD resistor is fabricated adjacent the bonding area, and at least a second ESD resistor is fabricated adjacent the first ESD resistor and the bonding area. The bonding pad extends beyond the bonding area to connect to the first ESD resistor and to the at least second ESD resistor, thereby providing at least two input ESD circuits for at least one current consuming electronic circuit from the single bonding pad.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: February 19, 2008
    Assignee: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Patent number: 7208987
    Abstract: A reset initialization structure and method is described. A power on reset pulse is utilized to force the state of system reset during intervals of Vcc which otherwise would result in indeterminate reset states. Operation is adaptable to include all DC power systems. The reset initialization structure provides operational protection during power up and power down conditions.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: April 24, 2007
    Assignee: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Patent number: 6717292
    Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: April 6, 2004
    Assignee: STMicroelectronics, Inc.
    Inventors: Tom Youssef, David Charles McClure
  • Publication number: 20030030329
    Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.
    Type: Application
    Filed: January 15, 2002
    Publication date: February 13, 2003
    Inventors: Tom Youssef, David Charles McClure
  • Patent number: 6518746
    Abstract: An integrated circuit structure provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The test mode structure of the IC memory device has a number of bipolar transistors, a number of ETD transistors coupled to the bipolar transistors, and a logic element coupled to the bipolar and ETD transistors at a node. The ETD transistors operate to ensure that the emitter of corresponding bipolar transistors have a voltage of Vb−Vbe.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: February 11, 2003
    Assignee: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Patent number: 6486007
    Abstract: A method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: November 26, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: Tsiu Chiu Chan, Mehdi Zamanian, David Charles McClure
  • Patent number: 6365991
    Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: April 2, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: Tom Youssef, David Charles McClure
  • Publication number: 20020028548
    Abstract: A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.
    Type: Application
    Filed: July 20, 2001
    Publication date: March 7, 2002
    Applicant: STMicroelectronics, Inc.
    Inventors: Tsiu Chiu Chan, Mehdi Zamanian, David Charles McClure
  • Publication number: 20010054909
    Abstract: An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.
    Type: Application
    Filed: August 17, 2001
    Publication date: December 27, 2001
    Applicant: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Patent number: 6310485
    Abstract: An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: October 30, 2001
    Assignee: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Patent number: 6295224
    Abstract: A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: September 25, 2001
    Assignee: STMicroelectronics, Inc.
    Inventors: Tsiu Chiu Chan, Mehdi Zamanian, David Charles McClure
  • Patent number: 6262617
    Abstract: A semiconductor device is provided which has a plurality of output drivers whose slew rates are differentially controlled. The slew rates of the output drivers are controlled by a control means such that the slew rate of at least one of the output drivers is different than the slew rate of another output driver. Preferably, the slew rates are differentially controlled such that an output driver that drives a signal that reaches an output pin of a semiconductor package later slews at a faster rate than an output driver that drives a signal that reaches an output pin of a semiconductor package earlier. In this way all of the output pins of a semiconductor package can be driven to change states at approximately the same time. The slew rates of the output drivers can be differentially controlled through the utilization of programmable resistors.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: July 17, 2001
    Assignee: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Patent number: 6252447
    Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: June 26, 2001
    Assignee: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Patent number: 6101618
    Abstract: A method and circuit for testing a packaged semiconductor memory device allow the acquisition of information on redundant elements by performing one of three possible redundancy rollcall tests on the packaged memory chip. By stimulating the packaged device's pins, the memory chip is set in one of the three test modes. In the first test mode, a preset signal indicating redundancy is sensed and the state of an output pin is changed. In the second test mode, memory array rows are sequentially addressed and the state of an output pin is changed when a redundant row is addressed. In the third test, array columns are sequentially addressed and, when a redundant column is addressed, the state of the output pin to which the redundant column is mapped is changed.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: August 8, 2000
    Assignee: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Patent number: 6075742
    Abstract: An integrated circuit and associated method for switching from a power supply to a battery are provided. The integrated circuit preferably includes a memory circuit responsive to an external power supply and to a battery for storing data therein and a sleep mode latching circuit connected to the memory circuit for latching the memory circuit in a reduced power sleep mode condition so as to reduce power usage of a battery and a non-sleep mode operating condition so as to allow normal operation of the memory circuit by a power supply. The integrated circuit preferably also includes a sleep mode latch locking circuit connected to the sleep mode latching circuit and the memory circuit and responsive to a power supply for locking the sleep mode latching circuit in the non-sleep mode operating condition when power supplied from the power supply falls below a predetermined threshold so that the memory circuit is inhibited from inadvertently entering the reduced power sleep mode condition.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: June 13, 2000
    Assignee: STMicroelectronics, Inc.
    Inventors: Tom Youssef, David Charles McClure
  • Patent number: RE40282
    Abstract: An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily every cycle of the integrated circuit device. Second, a node of the integrated circuit device is re-initialized every cycle if it is not forced by a super voltage indicative of test mode entry. Both of these responses prevent accidental entry of the integrated circuit device into the test mode. If the integrated circuit device is supposed to be in the test mode, it stays in the test mode. If, however, the integrated circuit device is not intended to be in the test mode, the ETD pulse forces the integrated circuit device out of the test mode. Subsequent entry into the test mode of the device is permitted if conditions for entry into the test mode have otherwise been met.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: April 29, 2008
    Assignee: STMicroelectronics, Inc.
    Inventor: David Charles McClure
  • Patent number: RE41337
    Abstract: The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated internal clock signal) is internally clocked. As the clock signal goes to a low logic state upon power-up of the device, a master latch (flip-flop) flip-flop element of the integrated circuit device is loaded with data and is allowed to conduct; a slave latch (flip-flop) flip-flop element of the integrated circuit device does not conduct. As the clock signal goes to a high logic state, the data in the master latch is latched. Also upon the high logic state of the clock, the slave latch element is loaded with data and is allowed to conduct.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: May 18, 2010
    Assignee: STMicroelectronics, Inc.
    Inventor: David Charles McClure