Abstract: A buck-type switched-mode power supply includes a switching cell formed by a first switch configured to be periodically set to the on state by a first control signal modulated by a modulation of pulse-width or pulse-frequency modulation type. An amplifier generates an error voltage representative of a difference between a reference voltage and an output voltage of the power supply intended to be applied to the input of the amplifier. A delay circuit applies a delay to the first control signal to decreasing a difference between the error voltage and the reference voltage. A delay modulation circuit modulates the value of the delay according to a difference between the error voltage and the reference voltage.

Abstract: An asynchronous finite state machine has states coupled by transitions each implemented by a flip-flop. Each flip-flop supplies a bit of a state of arrival of the corresponding transition, and receives a bit of an initial state of this transition on its data input and a first signal dedicated to the flip-flop on its control input. A circuit supplies, for each transition, a second signal of request for the transition. Another circuit generates based on the second signals, at each request for a transition and in the absence of a pulse of the first signals, a pulse of the first signal dedicated to the flip-flop of this transition, and a pulse of the first signal dedicated to each flip-flop supplying a bit to the flip-flop of the transition.

Abstract: A buck switching converter is calibrated using a method which alternates between first and second calibration phases. During each first calibration phase: a time period of low-side switch on state is kept constant and, for each current pulse in an inductor, a sign of a value of the current at the end of the time period of on state of the low-side switch is determined. Modification of a time period of high-side switch on state is made based on the determined sign. During each second calibration phase: a time period of high-side switch on state is kept constant and, for each current pulse in the inductor, a value of the current at the end of the time period of on state of the high-side switch is compared with a target value. Modification of the time period of low-side switch on state is made based on the comparison.

Abstract: An asynchronous finite state machine has states coupled by transitions each implemented by a flip-flop. Each flip-flop supplies a bit of a state of arrival of the corresponding transition, and receives a bit of an initial state of this transition on its data input and a first signal dedicated to the flip-flop on its control input. A circuit supplies, for each transition, a second signal of request for the transition. Another circuit generates based on the second signals, at each request for a transition and in the absence of a pulse of the first signals, a pulse of the first signal dedicated to the flip-flop of this transition, and a pulse of the first signal dedicated to each flip-flop supplying a bit to the flip-flop of the transition.

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.

Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between a first rail configured to receive a supply voltage and a first node; and an inductance coupled between the first node and a second node configured to deliver an output voltage, wherein, at each operating cycle of the converter, the first transistor is maintained in the on state for a first time period proportional to the inverse of a voltage difference between the supply voltage and the output voltage.

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.

Abstract: An embodiment voltage converter includes a first transistor and a second transistor coupled in series, and a first circuit configured to control the first and second transistors. The control terminal of the second transistor is coupled to a first output of the first circuit by a second circuit configured to delay the control signals supplied at the first output by a first duration. The control terminal of the first transistor is coupled to a second output of the first circuit by a circuit configured to delay the control signals supplied at the second output, for a second period of each operating cycle, by a duration equal to twice the first duration and, during a second period of each operating cycle, by a duration equal to the first duration.

Abstract: A method for increasing performance of a voltage-buck switched-mode voltage regulator includes generating a first pulse-width modulation signal based on a clock signal, decreasing a frequency of the clock signal to form a modified clock signal, passing the modified clock signal to a digital modulation circuit as a regulated clock signal; and generating a second pulse-width modulation signal based on the regulated clock signal using the digital modulation circuit. The first pulse-width modulation signal includes a period T1 and an off duration D2 corresponding to a first duty cycle. The off duration D2 is an intrinsic pulse-width modulation signal generation latency. The second pulse-width modulation signal includes a period T2 and the off duration D2. The decreased frequency of the modified clock signal causes T2 to be greater than T1 such that a second duty cycle of the second pulse-width modulation signal is increased relative to the first duty cycle.

Abstract: In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.

Abstract: In an embodiment, a method for operating a voltage step-down switched mode power supply includes delivering an output voltage with an output stage having a power transistor that is cyclically made conducting by a first control signal. In PWM mode, the method includes generating an error voltage based on the output voltage and a reference voltage, and applying a first delay on a first control signal. The first delay is determined so as to reduce a difference between the error voltage and the reference voltage.

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.

Abstract: An embodiment voltage converter includes a first transistor and a second transistor coupled in series, and a first circuit configured to control the first and second transistors. The control terminal of the second transistor is coupled to a first output of the first circuit by a second circuit configured to delay the control signals supplied at the first output by a first duration. The control terminal of the first transistor is coupled to a second output of the first circuit by a circuit configured to delay the control signals supplied at the second output, for a second period of each operating cycle, by a duration equal to twice the first duration and, during a second period of each operating cycle, by a duration equal to the first duration.

Abstract: In an embodiment, A device includes an operational amplifier and a feedback loop. The feedback loop is coupled between a first input of the operational amplifier and an output of the operational amplifier. The feedback loop is controllable according to a saturation of the operational amplifier. In one example, the device is incorporated in a microcontroller.

Abstract: A method for increasing performance of a voltage-buck switched-mode voltage regulator includes generating a first pulse-width modulation signal based on a clock signal, decreasing a frequency of the clock signal to form a modified clock signal, passing the modified clock signal to a digital modulation circuit as a regulated clock signal; and generating a second pulse-width modulation signal based on the regulated clock signal using the digital modulation circuit. The first pulse-width modulation signal includes a period T1 and an off duration D2 corresponding to a first duty cycle. The off duration D2 is an intrinsic pulse-width modulation signal generation latency. The second pulse-width modulation signal includes a period T2 and the off duration D2. The decreased frequency of the modified clock signal causes T2 to be greater than T1 such that a second duty cycle of the second pulse-width modulation signal is increased relative to the first duty cycle.

Abstract: In an embodiment, a method for operating a voltage step-down switched mode power supply includes delivering an output voltage with an output stage having a power transistor that is cyclically made conducting by a first control signal. In PWM mode, the method includes generating an error voltage based on the output voltage and a reference voltage, and applying a first delay on a first control signal. The first delay is determined so as to reduce a difference between the error voltage and the reference voltage.

Abstract: A method can be used for regulating a pulse-width modulation signal that is driving a voltage-buck switched-mode voltage regulator. The method includes comparing an input voltage of the switched-mode voltage regulator with a threshold voltage. The frequency of the pulse-width modulation signal is decreased when the input voltage is lower than the threshold voltage. The frequency is not decreased when the input voltage is not lower than the threshold voltage.

Abstract: In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.

Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between a first rail configured to receive a supply voltage and a first node; and an inductance coupled between the first node and a second node configured to deliver an output voltage, wherein, at each operating cycle of the converter, the first transistor is maintained in the on state for a first time period proportional to the inverse of a voltage difference between the supply voltage and the output voltage.