Patents by Inventor David Chesneau
David Chesneau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230387803Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventor: David Chesneau
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Patent number: 11750095Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between a first rail configured to receive a supply voltage and a first node; and an inductance coupled between the first node and a second node configured to deliver an output voltage, wherein, at each operating cycle of the converter, the first transistor is maintained in the on state for a first time period proportional to the inverse of a voltage difference between the supply voltage and the output voltage.Type: GrantFiled: October 23, 2020Date of Patent: September 5, 2023Assignee: STMicroelectronics (Grenoble 2) SASInventors: Helene Esch, Mathilde Sie, David Chesneau, Eric Feltrin
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Patent number: 11750096Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.Type: GrantFiled: July 29, 2021Date of Patent: September 5, 2023Assignee: STMicroelectronics (Grenoble 2) SASInventor: David Chesneau
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Patent number: 11742755Abstract: An embodiment voltage converter includes a first transistor and a second transistor coupled in series, and a first circuit configured to control the first and second transistors. The control terminal of the second transistor is coupled to a first output of the first circuit by a second circuit configured to delay the control signals supplied at the first output by a first duration. The control terminal of the first transistor is coupled to a second output of the first circuit by a circuit configured to delay the control signals supplied at the second output, for a second period of each operating cycle, by a duration equal to twice the first duration and, during a second period of each operating cycle, by a duration equal to the first duration.Type: GrantFiled: July 29, 2021Date of Patent: August 29, 2023Assignee: STMicroelectronics (Grenoble 2) SASInventor: David Chesneau
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Patent number: 11575306Abstract: A method for increasing performance of a voltage-buck switched-mode voltage regulator includes generating a first pulse-width modulation signal based on a clock signal, decreasing a frequency of the clock signal to form a modified clock signal, passing the modified clock signal to a digital modulation circuit as a regulated clock signal; and generating a second pulse-width modulation signal based on the regulated clock signal using the digital modulation circuit. The first pulse-width modulation signal includes a period T1 and an off duration D2 corresponding to a first duty cycle. The off duration D2 is an intrinsic pulse-width modulation signal generation latency. The second pulse-width modulation signal includes a period T2 and the off duration D2. The decreased frequency of the modified clock signal causes T2 to be greater than T1 such that a second duty cycle of the second pulse-width modulation signal is increased relative to the first duty cycle.Type: GrantFiled: April 28, 2021Date of Patent: February 7, 2023Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: David Chesneau, Francois Amiard, Helene Esch
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Patent number: 11539356Abstract: In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.Type: GrantFiled: October 23, 2020Date of Patent: December 27, 2022Assignee: STMicroelectronics (Grenoble 2) SASInventors: Helene Esch, David Chesneau
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Patent number: 11489446Abstract: In an embodiment, a method for operating a voltage step-down switched mode power supply includes delivering an output voltage with an output stage having a power transistor that is cyclically made conducting by a first control signal. In PWM mode, the method includes generating an error voltage based on the output voltage and a reference voltage, and applying a first delay on a first control signal. The first delay is determined so as to reduce a difference between the error voltage and the reference voltage.Type: GrantFiled: February 24, 2021Date of Patent: November 1, 2022Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventor: David Chesneau
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Publication number: 20220038005Abstract: An embodiment voltage converter includes a first transistor and a second transistor coupled in series, and a first circuit configured to control the first and second transistors. The control terminal of the second transistor is coupled to a first output of the first circuit by a second circuit configured to delay the control signals supplied at the first output by a first duration. The control terminal of the first transistor is coupled to a second output of the first circuit by a circuit configured to delay the control signals supplied at the second output, for a second period of each operating cycle, by a duration equal to twice the first duration and, during a second period of each operating cycle, by a duration equal to the first duration.Type: ApplicationFiled: July 29, 2021Publication date: February 3, 2022Inventor: David Chesneau
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Publication number: 20220038004Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.Type: ApplicationFiled: July 29, 2021Publication date: February 3, 2022Inventor: David Chesneau
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Patent number: 11171565Abstract: In an embodiment, A device includes an operational amplifier and a feedback loop. The feedback loop is coupled between a first input of the operational amplifier and an output of the operational amplifier. The feedback loop is controllable according to a saturation of the operational amplifier. In one example, the device is incorporated in a microcontroller.Type: GrantFiled: September 26, 2019Date of Patent: November 9, 2021Assignee: STMicroelectronics (Grenoble 2) SASInventors: David Chesneau, Helene Esch, Francois Amiard
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Publication number: 20210249954Abstract: A method for increasing performance of a voltage-buck switched-mode voltage regulator includes generating a first pulse-width modulation signal based on a clock signal, decreasing a frequency of the clock signal to form a modified clock signal, passing the modified clock signal to a digital modulation circuit as a regulated clock signal; and generating a second pulse-width modulation signal based on the regulated clock signal using the digital modulation circuit. The first pulse-width modulation signal includes a period T1 and an off duration D2 corresponding to a first duty cycle. The off duration D2 is an intrinsic pulse-width modulation signal generation latency. The second pulse-width modulation signal includes a period T2 and the off duration D2. The decreased frequency of the modified clock signal causes T2 to be greater than T1 such that a second duty cycle of the second pulse-width modulation signal is increased relative to the first duty cycle.Type: ApplicationFiled: April 28, 2021Publication date: August 12, 2021Inventors: David Chesneau, Francois Amiard, Helene Esch
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Publication number: 20210184580Abstract: In an embodiment, a method for operating a voltage step-down switched mode power supply includes delivering an output voltage with an output stage having a power transistor that is cyclically made conducting by a first control signal. In PWM mode, the method includes generating an error voltage based on the output voltage and a reference voltage, and applying a first delay on a first control signal. The first delay is determined so as to reduce a difference between the error voltage and the reference voltage.Type: ApplicationFiled: February 24, 2021Publication date: June 17, 2021Inventor: David Chesneau
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Patent number: 11011983Abstract: A method can be used for regulating a pulse-width modulation signal that is driving a voltage-buck switched-mode voltage regulator. The method includes comparing an input voltage of the switched-mode voltage regulator with a threshold voltage. The frequency of the pulse-width modulation signal is decreased when the input voltage is lower than the threshold voltage. The frequency is not decreased when the input voltage is not lower than the threshold voltage.Type: GrantFiled: September 13, 2019Date of Patent: May 18, 2021Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: David Chesneau, Francois Amiard, Helene Esch
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Publication number: 20210126535Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between a first rail configured to receive a supply voltage and a first node; and an inductance coupled between the first node and a second node configured to deliver an output voltage, wherein, at each operating cycle of the converter, the first transistor is maintained in the on state for a first time period proportional to the inverse of a voltage difference between the supply voltage and the output voltage.Type: ApplicationFiled: October 23, 2020Publication date: April 29, 2021Inventors: Helene Esch, Mathilde Sie, David Chesneau, Eric Feltrin
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Publication number: 20210126536Abstract: In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.Type: ApplicationFiled: October 23, 2020Publication date: April 29, 2021Inventors: Helene Esch, David Chesneau
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Patent number: 10992228Abstract: A method includes switching a switching circuit of the switched-mode power supply in a synchronous mode by turning on and off switches of the switching circuit in synchrony with a clock signal, wherein the switching circuit is coupled to an inductive element, and wherein the synchronous mode comprises a charging phase and a discharging phase; switching the switching circuit in an asynchronous mode by turning on and off switches of the switching circuit without being synchronized with the clock signal, wherein the asynchronous mode comprises a charging phase and a discharging phase; charging the inductive element during the charging phase of the synchronous mode; discharging the inductive element during the discharging phase of the synchronous mode; charging the inductive element during the charging phase of the asynchronous mode; and discharging the inductive element during the discharging phase of the asynchronous mode.Type: GrantFiled: March 16, 2020Date of Patent: April 27, 2021Assignee: STMicroelectronics (Grenoble 2) SASInventors: David Chesneau, Francois Amiard
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Patent number: 10944324Abstract: In an embodiment, a method for operating a voltage step-down switched mode power supply includes delivering an output voltage with an output stage having a power transistor that is cyclically made conducting by a first control signal. In PWM mode, the method includes generating an error voltage based on the output voltage and a reference voltage, and applying a first delay on a first control signal. The first delay is determined so as to reduce a difference between the error voltage and the reference voltage.Type: GrantFiled: October 11, 2019Date of Patent: March 9, 2021Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventor: David Chesneau
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Patent number: 10812058Abstract: A method for controlling operation of a comparator that includes an amplifier that is connected at an input of the comparator includes neutralizing any change of state of a signal output by the comparator starting from each moment in time at which the change of state of the output signal occurs and lasting for a duration of propagation to compensate for a duration of propagation of signals within the amplifier.Type: GrantFiled: July 22, 2019Date of Patent: October 20, 2020Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (GRENOBLE 2) SASInventors: Vincent Binet, David Chesneau
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Publication number: 20200220462Abstract: A method includes switching a switching circuit of the switched-mode power supply in a synchronous mode by turning on and off switches of the switching circuit in synchrony with a clock signal, wherein the switching circuit is coupled to an inductive element, and wherein the synchronous mode comprises a charging phase and a discharging phase; switching the switching circuit in an asynchronous mode by turning on and off switches of the switching circuit without being synchronized with the clock signal, wherein the asynchronous mode comprises a charging phase and a discharging phase; charging the inductive element during the charging phase of the synchronous mode; discharging the inductive element during the discharging phase of the synchronous mode; charging the inductive element during the charging phase of the asynchronous mode; and discharging the inductive element during the discharging phase of the asynchronous mode.Type: ApplicationFiled: March 16, 2020Publication date: July 9, 2020Inventors: David Chesneau, Francois Amiard
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Patent number: 10644597Abstract: A method includes switching a switching circuit of the switched-mode power supply in a synchronous mode by turning on and off switches of the switching circuit in synchrony with a clock signal, wherein the switching circuit is coupled to an inductive element, and wherein the synchronous mode comprises a charging phase and a discharging phase; switching the switching circuit in an asynchronous mode by turning on and off switches of the switching circuit without being synchronized with the clock signal, wherein the asynchronous mode comprises a charging phase and a discharging phase; charging the inductive element during the charging phase of the synchronous mode; discharging the inductive element during the discharging phase of the synchronous mode; charging the inductive element during the charging phase of the asynchronous mode; and discharging the inductive element during the discharging phase of the asynchronous mode.Type: GrantFiled: December 17, 2018Date of Patent: May 5, 2020Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: David Chesneau, Francois Amiard