Patents by Inventor David Chung

David Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050128846
    Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
    Type: Application
    Filed: December 31, 2004
    Publication date: June 16, 2005
    Inventors: Afshin Momtaz, Xin Wang, Jun Cao, Armond Hairapetian, David Chung
  • Publication number: 20050122815
    Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
    Type: Application
    Filed: December 30, 2004
    Publication date: June 9, 2005
    Inventors: Afshin Momtaz, Xin Wang, Jun Cao, Armond Hairapetian, David Chung
  • Publication number: 20050117428
    Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
    Type: Application
    Filed: December 31, 2004
    Publication date: June 2, 2005
    Inventors: Afshin Momtaz, Xin Wang, Jun Cao, Armond Hairapetian, David Chung
  • Publication number: 20050107536
    Abstract: The invention relates to new polymerization processes including diluents including hydrofluorocarbons and their use to produce novel polymers with new sequence distributions. In particular, the invention relates to copolymers of an isoolefin, preferably isobutylene, and a multiolefin, preferably a conjugated diene, more preferably isoprene, with new sequence distributions.
    Type: Application
    Filed: December 10, 2004
    Publication date: May 19, 2005
    Inventors: Timothy Shaffer, David Chung
  • Publication number: 20050101751
    Abstract: The invention relates to new polymerization processes including diluents including hydrofluorocarbons and their use to produce novel halogenated polymers with new sequence distributions. In particular, the invention relates to halogenated copolymers of an isoolefin, preferably isobutylene, and a multiolefin, preferably a conjugated diene, more preferably isoprene, with new sequence distributions.
    Type: Application
    Filed: December 10, 2004
    Publication date: May 12, 2005
    Inventors: Timothy Shaffer, David Chung
  • Publication number: 20050083455
    Abstract: A polymer memory system stores digital data in dipole moments of polymer memory cells. Apparatus is disclosed having polymer memory cells provided within an LCD display chamber. Embodiments provide for a high degree of integration the polymer memory system and a display system by providing polymer memory cells within the chamber. The memory cells may be located in non-viewable regions of the chamber. Thus, the memory cells provide only limited interference with the image-bearing functions of the display (if they interfere at all) but provide an extra dimension of functionality to the display.
    Type: Application
    Filed: October 16, 2003
    Publication date: April 21, 2005
    Inventor: David Chung
  • Publication number: 20050062546
    Abstract: A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating the count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.
    Type: Application
    Filed: November 2, 2004
    Publication date: March 24, 2005
    Inventor: David Chung
  • Patent number: 6866865
    Abstract: Oral progesterone unit dosage forms comprising micronized progesterone and a solid polymeric carrier are provided. The dosage forms, upon oral administration, provide a therapeutically effective blood level of progesterone to a subject. The therapeutically effective blood level of progesterone may range from about 0.1 ng/ml to about 400 ng/ml. The dosage forms can be prepared for immediate as well as sustained release. The oral progesterone dosage form can be combined with an estrogen dosage form to provide combination hormone therapy.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: March 15, 2005
    Assignee: Watson Pharmaceuticals, Inc.
    Inventors: David Chung Hsia, Thomas Chun Ho, Domingo Yap Tan, Fredric B. Weihmuller
  • Publication number: 20050027058
    Abstract: The present invention includes blends of a halogenated elastomer such as a butyl rubber or an interpolymer of, on one embodiment, a C4 to C7 isomonoolefin, a para-methylstyrene and a para-(halomethylstyrene), the interpolymer having been pre-mixed with an exfoliating compound and clay, the entire blend forming a nanocomposite in one embodiment. The clay may or may not have undergone an additional exfoliating treatment prior to blending with the halogenated elastomer. The interpolymer/clay mixture forms a distinct phase in the nanocomposite blend of the invention. The blend of the invention has improved air barrier properties and is suitable as an air barrier.
    Type: Application
    Filed: May 29, 2002
    Publication date: February 3, 2005
    Inventors: Anthony Dias, Andy Tsou, David Chung, Weiqing Weng
  • Publication number: 20050027057
    Abstract: The present invention is a blend of an halogenated elastomer and a clay, desirably an exfoliated clay, to form a nanocomposite suitable for an air barrier. In one embodiment, the halogenated elastomer, is a polymer comprising C4 to C7 isoolefin derived units, a para-methylstyrene derived units, and para-(halomethylstyrene) derived units. In another embodiment, the halogenated elastomer is a butyl-type rubber. The clay may or may not have an additional exfoliating treatment present prior to blending with the interpolymer. The interpolymer/clay mixture forms a distinct phase in the nanocomposite blend of the invention. The blend of the invention has improved air barrier properties and is suitable as an innerliner or innertube.
    Type: Application
    Filed: May 29, 2002
    Publication date: February 3, 2005
    Inventors: Anthony Dias, Andy Tsou, David Chung, Weiqing Weng, Caiguo Gong
  • Patent number: 6816490
    Abstract: A statistical learning technique in a multi-port bridge for a local area network (LAN). In response to data packets received by the multi-port bridge, learning operations are performed for updating a look-up table in the multi-port bridge. The look-up table is also utilized for identifying an appropriate destination port for each data packet by performing a look-up operation. A learning operation, however, is performed only in response to selected ones of the data packets. A statistical learning controller determines whether a received data packet is a broadcast or uni-cast packet. If the packet is a broadcast or multi-cast packet, the statistical learning controller forwards a request for a learning operation. Upon being granted, the look-up table is updated. It the packet is a uni-cast packet, the statistical learning controller forwards a request for a learning operation only if (m) uni-cast packets have been received since a prior learning operation was performed for a uni-cast packet.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: November 9, 2004
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: David Chung
  • Publication number: 20040156250
    Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 12, 2004
    Applicant: Broadcom Corporation
    Inventors: Afshin Momtaz, Xin Wang, Jun Cao, Armond Hairapetian, David Chung
  • Publication number: 20040158657
    Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 12, 2004
    Applicant: Broadcom Corporation
    Inventors: Afshin Momtaz, Xin Wang, Jun Cao, Armond Hairapetian, David Chung
  • Patent number: 6751225
    Abstract: The invention is a port in a multi-port bridge for a local area network having a vector buffer for storing vectors relating to the routing of data packets received in the port. The bridge includes a plurality of ports coupled a data bus and to a look-up bus. A look-up table coupled to the look-up bus correlates destination node addresses from each packet to an appropriate destination port. In addition, a packet buffer is coupled to the data bus for temporarily storing data packets. When a packet is received into a receive buffer of a source port, a destination and source address included in the packet are utilized to update the look-up table and to identify the appropriate destination port for the packet. This is preferably performed by the source port communicating with the look-up table via the look-up bus. Once the destination port has been identified, the identification of the destination port is stored in the receive vector for the packet.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: June 15, 2004
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: David Chung
  • Patent number: 6744728
    Abstract: A method of optimizing a data path in a multi-port bridge for a local area network (LAN) includes steps of: identifying a data path through the multi-port bridge wherein the data path includes a plurality of stages in a serial arrangement, wherein each stage performs a corresponding operation on data received from the LAN by the multi-port bridge; identifying a stage in the data path wherein the identified stage requires a period of time to perform its corresponding operation which is longer than any other stage; and subdividing the identified stage into two or more subdivided stages wherein the operations performed by the subdivided stages collectively perform the operation associated with the identified stage and wherein each of the two or more subdivided stages requires a period of time to perform its corresponding operation which is shorter than the period of time required for the identified stage to perform its corresponding operation.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: June 1, 2004
    Assignee: Sony Corporation & Sony Electronics, Inc.
    Inventor: David Chung
  • Patent number: 6738384
    Abstract: A technique for optimizing cut-through for broadcast and multi-cast data packets in a multi-port bridge for a local area network (LAN). The multi-port bridge includes a plurality of ports for communicating packets with an associated segment of the LAN. Each of the ports is coupled to a data bus for communicating packets among the ports. A packet buffer is coupled to the data bus for temporarily storing packets undergoing communication between the ports. At least one of the ports includes a transmit packet store for receiving packets to be transmitted by the port and a broadcast packet store for receiving broadcast and multi-cast packets to be transmitted by the port wherein the broadcast packet store receives a broadcast or multi-cast packet only when the transmit packet store is occupied. The transmit packet store can receive a packet from the packet buffer or at the same time the packet buffer receives the packet.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: May 18, 2004
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: David Chung
  • Publication number: 20040086003
    Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.
    Type: Application
    Filed: January 31, 2003
    Publication date: May 6, 2004
    Inventors: Vikram Natarajan, Kang Xiao, Mario Caresosa, Jay Proano, David Chung, Afshin Momtaz, Randy Stolaruk, Xin Wang, Namik Kocaman
  • Patent number: 6696854
    Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: February 24, 2004
    Assignee: Broadcom Corporation
    Inventors: Afshin Momtaz, Xin Wang, Jun Cao, Armond Hairapetian, David Chung
  • Patent number: 6617879
    Abstract: A transparently partitioned communication bus for interconnecting the ports of a multi-port bridge for a local area network. The communication bus is partitioned into a plurality of bus segments, each segment coupled to one or more ports of the multi-port bridge and including a same number (n) of signal lines. A controller pre-charges each signal line to a logic high voltage level by activating pre-charge transistors coupled between a voltage supply and a plurality of diodes, each diode coupled to a corresponding one of the signal lines. The pre-charging operation includes all the signal lines. The ports request access to the partitioned bus. A port having been granted access to the partitioned bus applies data to its associated bus segment. The transparent controller then senses the data applied by the port via sense lines.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: September 9, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: David Chung
  • Publication number: 20030143276
    Abstract: Oral progesterone unit dosage forms comprising micronized progesterone and a solid polymeric carrier are provided. The dosage forms, upon oral administration, provide a therapeutically effective blood level of progesterone to a subject. The therapeutically effective blood level of progesterone may range from about 0.1 ng/ml to about 400 ng/ml. The dosage forms can be prepared for immediate as well as sustained release. The oral progesterone dosage form can be combined with an estrogen dosage form to provide combination hormone therapy.
    Type: Application
    Filed: February 24, 2003
    Publication date: July 31, 2003
    Applicant: WATSON PHARMACEUTICALS, INC.
    Inventors: David Chung Hsia, Thomas Chun Ho, Domingo Yap Tan, Fredric C. Weihmuller