Abstract: There is provided a solder bump structure comprising an under bump metallurgy (UBM) layer, a first solder portion over the UBM layer, the first solder portion having a first composition, a barrier layer encapsulating the first solder portion, and a second solder portion over the barrier layer, the second solder portion having a second composition different from the first composition.

Abstract: A method for removing an electrical component from a substrate where the component is coupled to the substrate by connection elements. The method includes disposing liquid gallium (Ga) at or near an edge of the component and dispersing the liquid Ga between the substrate and the component such that the liquid Ga contacts one or more of the connection elements. The method also includes maintaining the liquid Ga between the substrate, component and one or more of the connection elements for a prescribed time period and removing the component from the substrate by applying a mechanical force to the component.

Abstract: A method for removing an electrical component from a substrate where the component is coupled to the substrate by connection elements. The method includes disposing liquid gallium (Ga) at or near an edge of the component and dispersing the liquid Ga between the substrate and the component such that the liquid Ga contacts one or more of the connection elements. The method also includes maintaining the liquid Ga between the substrate, component and one or more of the connection elements for a prescribed time period and removing the component from the substrate by applying a mechanical force to the component.

Abstract: A method for removing an electrical component from a substrate where the component is coupled to the substrate by connection elements. The method includes disposing liquid gallium (Ga) at or near an edge of the component and dispersing the liquid Ga between the substrate and the component such that the liquid Ga contacts one or more of the connection elements. The method also includes maintaining the liquid Ga between the substrate, component and one or more of the connection elements for a prescribed time period and removing the component from the substrate by applying a mechanical force to the component.

Abstract: A method for removing an electrical component from a substrate where the component is coupled to the substrate by connection elements. The method includes disposing liquid gallium (Ga) at or near an edge of the component and dispersing the liquid Ga between the substrate and the component such that the liquid Ga contacts one or more of the connection elements. The method also includes maintaining the liquid Ga between the substrate, component and one or more of the connection elements for a prescribed time period and removing the component from the substrate by applying a mechanical force to the component.

Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.

Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

Abstract: A plurality of through-substrate holes is formed in each of at least one substrate. Each through-substrate hole extends from a top surface of the at least one substrate to the bottom surface of the at least one substrate. The at least one substrate is held by a stationary chuck or a rotating chuck. Vacuum suction is provided to a set of through-substrate holes among the plurality of through-substrate holes through a vacuum manifold attached to the bottom surface of the at least one substrate. An injection mold solder head located above the top surface of the at least one substrate injects a solder material into the set of through-substrate holes to form a plurality of through-substrate solders that extend from the top surface to the bottom surface of the at least one substrate. The vacuum suction prevents formation of air bubbles or incomplete filling in the plurality of through-substrate holes.

Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.

Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.

Abstract: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips.

Abstract: A plurality of through-substrate holes is formed in each of at least one substrate. Each through-substrate hole extends from a top surface of the at least one substrate to the bottom surface of the at least one substrate. The at least one substrate is held by a stationary chuck or a rotating chuck. Vacuum suction is provided to a set of through-substrate holes among the plurality of through-substrate holes through a vacuum manifold attached to the bottom surface of the at least one substrate. An injection mold solder head located above the top surface of the at least one substrate injects a solder material into the set of through-substrate holes to form a plurality of through-substrate solders that extend from the top surface to the bottom surface of the at least one substrate. The vacuum suction prevents formation of air bubbles or incomplete filling in the plurality of through-substrate holes.

Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

Abstract: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips.

Abstract: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips.

Abstract: A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.

Abstract: A flip chip assembly having reduced stress and warpage comprises a flip chip package including an organic substrate and an integrated circuit chip, a temporary structure having a coefficient of thermal expansion that is substantially similar to a coefficient of thermal expansion of the integrated circuit chip, and a cap member coupled to a top side of the organic substrate. A bottom side of the integrated circuit chip is bonded to the top side of the organic substrate with controlled chip collapse columns. Additionally, a bottom side of the organic substrate is soldered to a top side of the temporary structure with solder interconnections that are applied to a plurality of solder pads on the top side of the temporary structure, the position of the solder pads on the temporary structure mirroring the position of a plurality of solder pads on the bottom side of the organic substrate.

Abstract: A method for reducing stress and warpage in flip chip packages comprising providing a flip chip package including an organic substrate, an integrated circuit chip, and a cap member, providing a temporary structure having a coefficient of thermal expansion that is substantially similar to a coefficient of thermal expansion of the integrated circuit chip, soldering a bottom side of the organic substrate to a top side of the temporary structure, bonding a bottom side of the integrated circuit chip to a top side of the organic substrate with controlled chip collapse columns, coupling the cap member to the top side of the organic substrate, applying force to the flip chip package in a first direction, and applying force to the temporary structure in a second direction opposite the first direction in order to shear the top side of the temporary structure from the bottom side of the organic substrate to remove the temporary structure from the flip chip package.