Patents by Inventor David Danovitch
David Danovitch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080185703Abstract: A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips.Type: ApplicationFiled: February 2, 2007Publication date: August 7, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luc Belanger, David Danovitch, John U. Knickerbocker
-
Publication number: 20070178625Abstract: Composite interconnect structure forming methods using injection molded solder are disclosed. The methods provide a mold having at least one opening formed therein with each opening including a member of a material dissimilar to a solder to be used to fill the opening, and then fill the remainder of each opening with solder to form the composite interconnect structure. The resulting composite interconnect structure can be leveraged to achieve a much larger variety of composite structures than exhibited by the prior art. For example, the material may be chosen to be more electrically conductive than the solder portion, more electromigration-resistant than the solder portion and/or more fatigue-resistant than the solder portion. In one embodiment, the composite interconnect structure can include an optical structure, or plastic or ceramic material.Type: ApplicationFiled: January 31, 2006Publication date: August 2, 2007Applicant: International Business Machines CorporationInventors: David Danovitch, Mukta Farooq, Michael Gaynes
-
Publication number: 20060289607Abstract: A method for constructing a composite solder transfer moldplate for flip chip wafer bumping of a substrate, comprising the steps of coating at least one polymer layer onto a first side of a transparent plate, the plate having a thermal expansion coefficient similar to that of the substrate; and forming a multiplicity of cavities in a polymer layer on one side of the plate, each cavity being for receiving solder. A moldplate made by the method. The structure has required behavior through temperature excursions between room temperature and various solder molten temperatures.Type: ApplicationFiled: June 28, 2005Publication date: December 28, 2006Inventors: Stephen Buchwalter, David Danovitch, Frank Egitto, Peter Gruber, Eric Perfecto, Da-Yuan Shih
-
Patent number: 7070087Abstract: The present invention relates to improvements in forming and transferring solder bumps for use in mounting integrated circuit substrates on chip carrier packages. A mold having cavities for the solder bumps is held in contact with a substrate and a compressible device. As the temperature is increased to melt the solder in the cavities, at an appropriate time and temperature, the compressible device is caused to decompress resulting in the mold separating from the substrate and leaving formed solder bumps on the contacts on the substrate. Various mechanisms are described to cause the force holding the mold and substrate together to decrease.Type: GrantFiled: December 3, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Guy Brouillette, David Danovitch, Jean-Paul Henry
-
Patent number: 7038462Abstract: Improved methods and apparatus is disclosed for electrical testing of electronic circuits such as those existing in microcircuit devices including chip carriers, printed circuit boards and substrates. The invention provides for the testing of the continuity of electronic circuits in progressively smaller devices having increased density of circuits and having pads closely spaced. A quasi-fluidized bed of conductive particles is provided for effectively contacting pads on a first side of a substrate. Pads on another side of the substrate which are connected to the pads on the first side are then contacted by a test device. The circuit interconnecting respective pads on the two sides of the substrate can then be assessed for electrical continuity.Type: GrantFiled: June 22, 2004Date of Patent: May 2, 2006Assignee: International Business Machines CorporationInventors: David Danovitch, Richard Langlois, Martin Lapointe, Robert-Paul Leclerc
-
Patent number: 6924171Abstract: Methods for fabricating microelectronic interconnection structures as well as the structures formed by the methods are disclosed which improve the manufacturing throughput for assembling flip chip semiconductor devices. The use of a bilayer of polymeric materials applied on the wafer prior to dicing eliminates the need for dispensing and curing underfill for each semiconductor at the package level, thereby improving manufacturing throughput and reducing cost.Type: GrantFiled: February 13, 2001Date of Patent: August 2, 2005Assignee: International Business Machines CorporationInventors: Stephen L. Buchwalter, David Danovitch, Fuad Elias Doany, Claudius Feger, Peter A. Gruber, Revathi Iyengar, Nancy C. LaBianca
-
Patent number: 6893799Abstract: A method to effectively deposit multi-component solders while remaining compatible with electroplating solder bumping process. A flip-chip solder bump is formed by using electroplated solder bump technology with the addition of wettable layer of metal or solder. The remainder of the required solder volume is deposited by Injection Molded Solder (IMS) technology. This method will accommodate certain metals, as well as trace amounts of alloying, that would be difficult or impossible to electroplate. The method also allows for electrical test between deposition of the wettable layer of solder and the bulk solder, providing the advantages of a more planar surface for probe contact, with very consistent height, less solder pick-up by the test probe and elimination of the post-probe solder reflow step.Type: GrantFiled: March 6, 2003Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: David Danovitch, Stephen Kilpatrick
-
Publication number: 20050062493Abstract: Improved methods and apparatus is disclosed for electrical testing of electronic circuits such as those existing in microcircuit devices including chip carriers, printed circuit boards and substrates. The invention provides for the testing of the continuity of electronic circuits in progressively smaller devices having increased density of circuits and having pads closely spaced. A quasi-fluidized bed of conductive particles is provided for effectively contacting pads on a first side of a substrate. Pads on another side of the substrate which are connected to the pads on the first side are then contacted by a test device. The circuit interconnecting respective pads on the two sides of the substrate can then be assessed for electrical continuity.Type: ApplicationFiled: June 22, 2004Publication date: March 24, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Danovitch, Richard Langlois, Martin Lapointe, Robert-Paul Leclerc
-
Publication number: 20040233638Abstract: In a microelectronic chip package for which grounding and thermal dissipation is desired, a cover is provided having an opening which is aligned with a contact on the substrate connected to ground potential. The cover is connected to the electronic device and the ground contact. This invention provides for a method and electronic package to overcome the difficulties encountered when attempting to simultaneously attach a cover to two different surfaces with two different adhesives.Type: ApplicationFiled: October 23, 2003Publication date: November 25, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Danovitch, Eric Duchesne
-
Patent number: 6819566Abstract: In a microelectronic chip package for which grounding and thermal dissipation is desired, a cover is provided having an opening which is aligned with a contact on the substrate connected to ground potential. The cover is connected to the electronic device and the ground contact. This invention provides for a method and electronic package to overcome the difficulties encountered when attempting to simultaneously attach a cover to two different surfaces with two different adhesives.Type: GrantFiled: October 23, 2003Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventors: David Danovitch, Eric Duchesne
-
Publication number: 20040214420Abstract: The present invention relates to improvements in forming and transferring solder bumps for use in mounting integrated circuit substrates on chip carrier packages. A mold having cavities for the solder bumps is held in contact with a substrate and a compressible device. As the temperature is increased to melt the solder in the cavities, at an appropriate time and temperature, the compressible device is caused to decompress resulting in the mold separating from the substrate and leaving formed solder bumps on the contacts on the substrate. Various mechanisms are described to cause the force holding the mold and substrate together to decrease.Type: ApplicationFiled: December 3, 2003Publication date: October 28, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy Brouillette, David Danovitch, Jean-Paul Henry
-
Publication number: 20040175657Abstract: A method to effectively deposit multi-component solders while remaining compatible with electroplating solder bumping process. A flip-chip solder bump is formed by using electroplated solder bump technology with the addition of wettable layer of metal or solder. The remainder of the required solder volume is deposited by Injection Molded Solder (IMS) technology. This method will accommodate certain metals, as well as trace amounts of alloying, that would be difficult or impossible to electroplate. The method also allows for electrical test between deposition of the wettable layer of solder and the bulk solder, providing the advantages of a more planar surface for probe contact, with very consistent height, less solder pick-up by the test probe and elimination of the post-probe solder reflow step.Type: ApplicationFiled: March 6, 2003Publication date: September 9, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Danovitch, Stephen Kilpatrick
-
Publication number: 20020109228Abstract: Methods for fabricating microelectronic interconnection structures as well as the structures formed by the methods are disclosed which improve the manufacturing throughput for assembling flip chip semiconductor devices. The use of a bilayer of polymeric materials applied on the wafer prior to dicing eliminates the need for dispensing and curing underfill for each semiconductor at the package level, thereby improving manufacturing throughput and reducing cost.Type: ApplicationFiled: February 13, 2001Publication date: August 15, 2002Inventors: Stephen L. Buchwalter, David Danovitch, Fuad Elias Doany, Claudius Feger, Peter A. Gruber, Revathi Iyengar, Nancy C. LaBianca
-
Publication number: 20020023945Abstract: A method for joining a multiplicity of multi-alloy solder columns to an electronic substrate and the structure formed by such method are disclosed. In the method, a mold plate equipped with a multiplicity of cavities is first filled by an injection molded solder technique with a high temperature solder forming a multiplicity of solder columns. The mold plate is then sandwiched between an extraction plate and a transfer plate by utilizing a multiplicity of displacement means equipped in the extraction plate to displace the multiplicity of solder columns from the mold plate into a multiplicity of apertures equipped in the transfer plate. The multiplicity of cavities in the transfer plate each has a straight opening and a flared opening. The flared opening is then filled with a low temperature solder paste to encapsulate one end of the high temperature solder column.Type: ApplicationFiled: May 22, 2001Publication date: February 28, 2002Applicant: International Business Machines CorporationInventors: Peter A. Gruber, Lannie R. Bolde, Guy P. Brouillette, James H. Covell, David Danovitch, Chon C. Lei
-
Patent number: 6276596Abstract: A method for joining a multiplicity of multi-alloy solder columns to an electronic substrate and the structure formed by such method are disclosed. In the method, a mold plate equipped with a multiplicity of cavities is first filled by an injection molded solder technique with a high temperature solder forming a multiplicity of solder columns. The mold plate is then sandwiched between an extraction plate and a transfer plate by utilizing a multiplicity of displacement means equipped in the extraction plate to displace the multiplicity of solder columns from the mold plate into a multiplicity of apertures equipped in the transfer plate. The multiplicity of cavities in the transfer plate each has a straight opening and a flared opening. The flared opening is then filled with a low temperature solder paste to encapsulate one end of the high temperature solder column.Type: GrantFiled: August 28, 2000Date of Patent: August 21, 2001Assignee: International Business Machines CorporationInventors: Peter A. Gruber, Lannie R. Bolde, Guy P. Brouillette, James H. Covell, David Danovitch, Chon C. Lei