Patents by Inventor David Ding-Chung Lu
David Ding-Chung Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9698080Abstract: A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.Type: GrantFiled: September 4, 2015Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chih Chiou, David Ding-Chung Lu
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Publication number: 20150380341Abstract: A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.Type: ApplicationFiled: September 4, 2015Publication date: December 31, 2015Inventors: Wen-Chih Chiou, David Ding-Chung Lu
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Patent number: 9130024Abstract: A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.Type: GrantFiled: March 12, 2012Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chih Chiou, David Ding-Chung Lu
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Patent number: 8237209Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate and a MIM capacitor over the substrate. The MIM capacitor includes a bottom plate, an insulating layer over the bottom plate, and a top plate over the insulating layer. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate and a metal-containing gate electrode free from polysilicon on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material and has a same thickness as the bottom plate.Type: GrantFiled: August 23, 2011Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Long Chang, David Ding-Chung Lu, Chia-Yi Chen, I-Lu Wu
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Publication number: 20120164789Abstract: A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.Type: ApplicationFiled: March 12, 2012Publication date: June 28, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chih Chiou, David Ding-Chung Lu
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Patent number: 8178289Abstract: A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lower-precision lithography mechanism. The exposures can be done in either order, and additional exposures can be included. The higher-precision lithography mechanism can be immersion lithography and the lower-precision lithography mechanism can be dry lithography.Type: GrantFiled: January 29, 2009Date of Patent: May 15, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei Shun Chen, Chin-Hsiang Lin, David Ding-Chung Lu
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Publication number: 20120090547Abstract: Provided is a system for vapor deposition of a coating material onto a semiconductor substrate. The system includes a chemical supply chamber, a supply nozzle operable to dispense vapor, and a heating element operable to provide heat to a substrate in-situ with the dispensing of vapor. The system may further include reaction chamber(s) and/or mixing chamber(s).Type: ApplicationFiled: December 27, 2011Publication date: April 19, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Chien-Wei Wang, David Ding-Chung Lu, Ching-Yu Chang
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Patent number: 8134235Abstract: A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.Type: GrantFiled: April 23, 2007Date of Patent: March 13, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Chih Chiou, David Ding-Chung Lu
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Patent number: 8105954Abstract: Provided is a method and system for vapor deposition of a coating material onto a semiconductor substrate. In an embodiment, photoresist is deposited. An in-situ baking process may be performed with the vapor deposition. In an embodiment, a ratio of chemical components of a material to be deposited onto the substrate is changed during the deposition. Therefore, a layer having a gradient chemical component distribution may be provided. In an embodiment, a BARC layer may be provided which includes a gradient chemical component distribution providing an n,k distribution through the layer. Other materials that may be vapor deposited include pattern freezing material.Type: GrantFiled: October 20, 2008Date of Patent: January 31, 2012Assignee: Aiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Wei Wang, David Ding-Chung Lu, Ching-Yu Chang
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Publication number: 20110309420Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate and a MIM capacitor over the substrate. The MIM capacitor includes a bottom plate, an insulating layer over the bottom plate, and a top plate over the insulating layer. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate and a metal-containing gate electrode free from polysilicon on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material and has a same thickness as the bottom plate.Type: ApplicationFiled: August 23, 2011Publication date: December 22, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Long Chang, David Ding-Chung Lu, Chia-Yi Chen, I-Lu Wu
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Patent number: 8053865Abstract: An integrated circuit structure combining air-gaps and metal-oxide-metal (MOM) capacitors is provided. The integrated circuit structure includes a semiconductor substrate; a first metallization layer over the semiconductor substrate; first metal features in the first metallization layer; a second metallization layer over the first metallization layer; second metal features in the second metallization layer, wherein the first and the second metal features are non-capacitor features; a MOM capacitor having an area in at least one of the first and the second metallization layers; and an air-gap in the first metallization layer and between the first metal features.Type: GrantFiled: March 10, 2008Date of Patent: November 8, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Long Chang, Ming-Shih Yeh, Chia-Yi Chen, David Ding-Chung Lu
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Patent number: 8022458Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.Type: GrantFiled: October 8, 2007Date of Patent: September 20, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Long Chang, David Ding-Chung Lu, Chia-Yi Chen, I-Lu Wu
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Patent number: 7760144Abstract: An integrated circuit structure includes a semiconductor chip including a top surface, a bottom surface, and a side surface; a metal seal ring adjacent the side surface; and an antenna including a seal-ring antenna. The seal-ring antenna includes at least a portion of the metal seal ring.Type: GrantFiled: August 4, 2008Date of Patent: July 20, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Long Chang, David Ding-Chung Lu, Shine Chung
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Publication number: 20100099267Abstract: Provided is a method and system for vapor deposition of a coating material onto a semiconductor substrate. In an embodiment, photoresist is deposited. An in-situ baking process may be performed with the vapor deposition. In an embodiment, a ratio of chemical components of a material to be deposited onto the substrate is changed during the deposition. Therefore, a layer having a gradient chemical component distribution may be provided. In an embodiment, a BARC layer may be provided which includes a gradient chemical component distribution providing an n,k distribution through the layer. Other materials that may be vapor deposited include pattern freezing material.Type: ApplicationFiled: October 20, 2008Publication date: April 22, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Wei Wang, David Ding-Chung Lu, Ching-Yu Chang
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Publication number: 20100026601Abstract: An integrated circuit structure includes a semiconductor chip including a top surface, a bottom surface, and a side surface; a metal seal ring adjacent the side surface; and an antenna including a seal-ring antenna. The seal-ring antenna includes at least a portion of the metal seal ring.Type: ApplicationFiled: August 4, 2008Publication date: February 4, 2010Inventors: Chung-Long Chang, David Ding-Chung Lu, Shine Chung
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Publication number: 20090224359Abstract: An integrated circuit structure combining air-gaps and metal-oxide-metal (MOM) capacitors is provided. The integrated circuit structure includes a semiconductor substrate; a first metallization layer over the semiconductor substrate; first metal features in the first metallization layer; a second metallization layer over the first metallization layer; second metal features in the second metallization layer, wherein the first and the second metal features are non-capacitor features; a MOM capacitor having an area in at least one of the first and the second metallization layers; and an air-gap in the first metallization layer and between the first metal features.Type: ApplicationFiled: March 10, 2008Publication date: September 10, 2009Inventors: Chung-Long Chang, Ming-Shin Yeh, Chia-Yi Chen, David Ding-Chung Lu
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Publication number: 20090136876Abstract: A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lower-precision lithography mechanism. The exposures can be done in either order, and additional exposures can be included. The higher-precision lithography mechanism can be immersion lithography and the lower-precision lithography mechanism can be dry lithography.Type: ApplicationFiled: January 29, 2009Publication date: May 28, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFUCTURING COMPANY, LTD.Inventors: Kuei Shun Chen, Chin-Hsiang Lin, David Ding-Chung Lu
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Publication number: 20090090951Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.Type: ApplicationFiled: October 8, 2007Publication date: April 9, 2009Inventors: Chung-Long Chang, David Ding-Chung Lu, Chia-Yi Chen, I-Lu Wu
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Patent number: 7501227Abstract: A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lower-precision lithography mechanism. The exposures can be done in either order, and additional exposures can be included. The higher-precision lithography mechanism can be immersion lithography and the lower-precision lithography mechanism can be dry lithography.Type: GrantFiled: August 31, 2005Date of Patent: March 10, 2009Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kuei Shun Chen, Chin-Hsiang Lin, David Ding-Chung Lu
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Publication number: 20080258309Abstract: A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.Type: ApplicationFiled: April 23, 2007Publication date: October 23, 2008Inventors: Wen-Chih Chiou, David Ding-Chung Lu