Abstract: Methods and systems for hardening a clocked latch against single event effects are disclosed. A system includes a first three-input OR gate, a first NAND gate, a second three-input OR gate, and a second NAND gate. The first three-input OR gate receives as inputs a clock signal, a first signal, and a redundant first signal. An output of the first three-input OR gate is connected to an input of the first NAND gate. The second three-input OR gate receives as inputs the clock signal, a second signal, and a redundant second signal. An output of the second three-input OR gate is connected to an input of the second NAND gate. A first output signal of the first NAND gate is connected to another input of the second NAND gate and a second output signal of the second NAND gate is connected to another input of the first NAND gate.

Abstract: A method for modeling a circuit layout to determine behavior responsive to a radiation event is set forth. The method includes identifying a first portion of the circuit layout that includes at least one body region of a MOS transistor in the circuit layout, the at least one region having a width substantially equal to that of the MOS transistor. A first model corresponding to the first portion of the circuit layout is selected. A second portion of the circuit layout that includes at least a first region within a drain of the MOS transistor in the circuit layout is identified and an appropriate second model corresponding to the second portion of the circuit layout is selected, wherein the at least one second model includes at least one parasitic bipolar transistor.

Abstract: A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block receives a first data input and second data input from redundant logic blocks or from logic blocks designed to provide complementary outputs. The decision block provides an output that is at a same logic level as the first data input if the two data inputs are at expected logic levels during normal operating conditions (i.e., no disturbances). The decision block provides an output that is at a same logic level as a previous output of the decision block if the two data inputs are not at expected logic levels during normal operating conditions.

Abstract: A system for communicating between integrated circuits is disclosed. The system includes a driver having an input and an output. In response to a logic transition from a first logic state to a second logic state at the driver input, the driver output transitions from a low-power condition, to a transmitting condition, to the low-power condition. The system also includes a receiver having an input and an output. The receiver detects the logic state of the transmitting condition at the driver output and latches it to the receiver output after the driver output returns to the low-power condition. The system also includes a transmission line, which connects the driver output to the receiver input.

Abstract: A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.

Abstract: Majority voting between triple redundant integrated circuits is used in order to provide an SEU hardened output signal. Accordingly, an input signal is processed in a predetermined manner to provide a first signal, the input signal is processed in the same manner to provide a second signal, and the input signal is also processed in the same manner to provide a third signal. A majority vote is taken between the first, second, and third signals by an SEU immune majority voter circuit, and an output signal is provided corresponding to the majority vote.

Abstract: A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.

Abstract: A first cold spare circuit has first and second transistors, and a second cold spare circuit has third and fourth transistors. The first transistor has a gate controlled by a function of a first chip. A second transistor has its source and drain connected in series with the source and drain of the first transistor between the output and a first potential terminal. A third transistor has a gate controlled by a function of a second chip. A fourth transistor has its source and drain connected in series with the source and drain of the third transistor between the output and a second potential terminal. A first control circuit controls the gate of the second transistor and a second control circuit controls the gate of the fourth transistor so as to turn on one of the second and fourth transistors at a time.

Abstract: A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.

Abstract: Majority voting between triple redundant integrated circuits is used in order to provide an SEU hardened output signal. Accordingly, an input signal is processed in a predetermined manner to provide a first signal, the input signal is processed in the same manner to provide a second signal, and the input signal is also processed in the same manner to provide a third signal. A majority vote is taken between the first, second, and third signals by an SEU immune majority voter circuit, and an output signal is provided corresponding to the majority vote.

Abstract: A threshold control circuit for CMOS transistors wherein the voltage on the body of an n-channel reference transistor is controlled with a feedback circuit to produce a positive voltage on the body and decrease the threshold of the reference transistor to a desired value and the voltage on the body of a p-channel reference transistor is controlled with a feedback circuit to produce a negative voltage on the body and decrease the threshold of the reference transistor to a desired value.

Abstract: A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic site, thereby allowing the stored state of a cell to be read.

Abstract: A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.

Abstract: Majority voting between triple redundant integrated circuits is used in order to provide an SEU hardened output signal. Accordingly, an input signal is processed in a predetermined manner to provide a first signal, the input signal is processed in the same manner to provide a second signal, and the input signal is also processed in the same manner to provide a third signal. A majority vote is taken between the first, second, and third signals by an SEU immune majority voter circuit, and an output signal is provided corresponding to the majority vote.

Abstract: An output buffer is provided in the form of a voltage follower having a positive input that receives a reference voltage, a negative input and an output coupled together, and a control input that turns the voltage follower on and off. The output is coupled to one side of a load. The output buffer may have one or more additional voltage followers. For example, the output buffer may include three additional voltage followers with all voltage followers arranged as a low voltage differential signal (LVDS) buffer.

Abstract: A threshold control circuit for CMOS transistors wherein the voltage on the body of an n-channel reference transistor is controlled with a feedback circuit to produce a positive voltage on the body and decrease the threshold of the reference transistor to a desired value and the voltage on the body of a p-channel reference transistor is controlled with a feedback circuit to produce a negative voltage on the body and decrease the threshold of the reference transistor to a desired value.

Abstract: A method and apparatus for storing data in a master flip flop, comprising in combination receiving a clock signal having a first and second state, storing a master data state in a master storage device having a master storage input and a master storage output, storing a master complement data state in a master complement storage device having a master complement storage input and a master storage complement output, receiving a data input signal by a transmission gate, receiving a complement data input signal by a complement transmission gate, overriding the master storage complement output with the data input signal when the clock is in the first state, overriding the master storage output with the complement data input signal when the clock is in the first state, disconnecting the master storage complement output from the data input signal when the clock is in the second state, and disconnecting the master storage output from the complement data input signal when the clock is in the second state.

Abstract: An CMOS ECL output buffer has a CMOS differential amplifier. A CMOS reference circuit supplies a reference to a reference input of the CMOS differential amplifier. The reference has a high-state value suitable for use by ECL. A CMOS feedback circuit couples a buffer output as negative feedback to a feedback input of the CMOS differential amplifier. A CMOS output circuit supplies an output of the CMOS differential amplifier as the buffer output in response to an input. The buffer output is provided to the ECL. Accordingly, the buffer output is low when the input is low, and the buffer output has the high-state value when the input is high.

Abstract: A CMOS ECL input buffer buffers signals from an ECL circuit to a CMOS circuit. The CMOS ECL input buffer has a CMOS differential amplifier. A CMOS input circuit is coupled between a buffer input that receives the ECL circuit and a first input of the CMOS differential amplifier. The CMOS input circuit couples an input signal to the first input of the CMOS differential amplifier, and the input signal has an input voltage swing. A reference circuit provides a reference to a second input of the CMOS differential amplifier. The reference is nominally set at substantially a midpoint of the input voltage swing. A CMOS output circuit is coupled between the output of the CMOS differential amplifier and the buffer output, and is arranged to provide an output signal to the buffer output. The output signal, in response to the CMOS differential amplifier, swings between a typical CMOS positive source voltage and ground as the input signal traverses the reference.

Abstract: An output buffer is provided in the form of a voltage follower having a positive input that receives a reference voltage, a negative input and an output coupled together, and a control input that turns the voltage follower on and off. The output is coupled to one side of a load. The output buffer may have one or more additional voltage followers. For example, the output buffer may include three additional voltage followers with all voltage followers arranged as a low voltage differential signal (LVDS) buffer.