Abstract: An output buffer is provided in the form of a voltage follower having a positive input that receives a reference voltage, a negative input and an output coupled together, and a control input that turns the voltage follower on and off. The output is coupled to one side of a load. The output buffer may have one or more additional voltage followers. For example, the output buffer may include three additional voltage followers with all voltage followers arranged as a low voltage differential signal (LVDS) buffer.

Abstract: A method and apparatus for storing data in a master flip flop, comprising in combination receiving a clock signal having a first and second state, storing a master data state in a master storage device having a master storage input and a master storage output, storing a master complement data state in a master complement storage device having a master complement storage input and a master storage complement output, receiving a data input signal by a transmission gate, receiving a complement data input signal by a complement transmission gate, overriding the master storage complement output with the data input signal when the clock is in the first state, overriding the master storage output with the complement data input signal when the clock is in the first state, disconnecting the master storage complement output from the data input signal when the clock is in the second state, and disconnecting the master storage output from the complement data input signal when the clock is in the second state.

Abstract: A latch and flip-flop are disclosed that have a reduced clock-to-q delay and/or a reduced setup time. This is preferably accomplished by providing both a data input signal and a complement data input signal to the latch or flip-flop. The data input signal and the complement data input signal are selectively connected to opposite sides of a pair of cross-coupled gates via a switch or the like. The switch is preferably controlled by an enable signal, such as a clock. With the switch elements enabled, the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal. Because the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal, the clock-to-q time may be reduced.

Abstract: A domino logic circuit and circuit family is disclosed that has reduced the capacitance on the evaluation node for increased performance. The domino logic circuit preferably includes an inverter, a pre-charge transistor, a logic block, and a pre-charge control transistor. One or both of the clocked transistors of conventional domino logic circuits are removed, and a single clocked transistor that controls the logic state of the output of the inverter is provided. This arrangement reduces or eliminates the series resistance in line with the logic block, reduces or eliminates the capacitance contributed by the clocked pre-charge transistor of conventional domino logic circuits, and reduces the size and thus the capacitance contributed by one or more of the transistor of the inverter.

Abstract: A latch and flip-flop are disclosed that have a reduced clock-to-q delay and/or a reduced setup time. This is preferably accomplished by providing both a data input signal and a complement data input signal to the latch or flip-flop. The data input signal and the complement data input signal are selectively connected to opposite sides of a pair of cross-coupled gates via a switch or the like. The switch is preferably controlled by an enable signal, such as a clock. With the switch elements enabled, the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal. Because the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal, the clock-to-q time may be reduced.

Abstract: A logic family is disclosed that produces the same advantages as Dual Pass-Transistor Logic (DPL), but uses fewer transistors and provides increased performance relative to DPL. This is accomplished by removing one or more of the transistors from a typical DPL gate. Because fewer transistors are used, circuits constructed in accordance with the present invention may have increased performance and increased density relative to DPL.

Abstract: A non-volatile latch having a power supply terminal and a ground terminal is disclosed. The non-volatile latch includes a pair of cross-coupled inverter elements each having a power supply terminal and a ground terminal. Magneto-resistive elements are interposed between the power supply terminals of both cross-coupled inverter elements and the power supply terminal of the non-volatile latch. In addition, magneto-resistive elements are interposed between the ground terminals of both cross-coupled inverter elements and the ground terminal of the non-volatile latch. By including magneto-resistive elements in each supply line, the effects of transistor parameter variation can be minimized.

Abstract: A logic circuit includes a potential coupled to a node and a first transistor coupled between a first input and the output with its gate coupled to the node. At least a second transistor is coupled between the node and ground with its gate coupled to a second input. At least a third transistor is coupled between the output terminal and ground with its gate connected to the second input.

Abstract: A gate having a complementary input stage (12) and an N-channel push-pull output stage (14). This circuit is faster than a circuit with a single complementary stage because the N-channel transistors can pull-up or pull down the load capacitance more quickly than P-channel transistors can. A fundamental aspect of the invention is the replacement of the input P-channel input transistors (182) of standard logic circuits, particularly CMOS, with a two N-channel and one P-channel transistor input circuit (184). The circuit may use field effect transistors exclusively as elements.

Abstract: An improved FET capacitance driver logic circuit having an inverter feedback stage 22 connected from output to input of output FET 23 to allow the output FET to have a large capacitance charging current surge followed by a reduced conduction thereafter.

Abstract: A system is provided for dynamically detecting and providing an electronic output representative of changes in the position of a fuel injection element in an internal combustion engine. The system includes an electronic circuit having a sensor for sensing a change in a magnetic field external to the circuit, and providing an output representative of the change. Circuit elements are electronically coupled with the output of the sensor for providing an output indicating the presence of the magnetic field change. A nulling circuit is provided for nulling the electronic circuit responsive to the sensor output, to thereby compensate for ambient magnetic fields, temperature and process variations. Exceptionally low current circuit characteristics are achieved in an integrated circuit configuration and geometry having very low junction leakage characteristics.

Abstract: A logic family is provided capable of accomplishing a logic function for each transistor used, i.e., one transistor per logic gate. A plurality of logic gate types are shown, each capable of a different logic function. Nonlinear loads are used in the logic gate circuits.

Abstract: A logic family is provided capable of accomplishing a logic function for each transistor used, i.e. one transistor per logic gate. A plurality of logic gate types as shown, each capable of a different logic function.

Abstract: Transition circuits are provided for interfacing logic gate circuits from different kinds of logic gate families where the characteristic logic state voltage levels differ between the families as do the separations between these logic state voltage levels as they occur in these logic families.

Abstract: A logic family is provided capable of accomplishing a logic function for each transistor used, i.e. one transistor per logic gate. A plurality of logic gate types are shown, each capable of a different logic function. These logic gate types can be connected with one another to provide the "DOT--AND" logic function.

Abstract: An electromagnetic radiation intensity comparator is disclosed for providing an indication of differences between electromagnetic radiation intensities occurring at different photodetectors.

Abstract: A logic family is provided capable of accomplishing a logic function for each transistor used, i.e. one transistor per logic gate. A plurality of logic gate types are shown, each capable of a different logic function. These logic gate types can be connected with one another to provide the "DOT--AND" logic function.

Abstract: A novel voltage reference regulator is disclosed which operates in a relatively low voltage environment so as to effectively control an electrical potential subject to some relatively large current fluctuations. The voltage reference regulator comprises a voltage amplifier operating in conjunction with a low impedance output circuit so as to counteract the current fluctuations. The voltage amplifier consists of two differential amplifying stages whereas the output circuit comprises a dual transistor Darlington configuration.

Abstract: A logic family is provided capable of accomplishing a logic function for each transistor used, i.e. one transistor per logic gate. A plurality of logic gate types are shown, each capable of a different logic function.