Patents by Inventor David E. Kotecki
David E. Kotecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6753252Abstract: Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.Type: GrantFiled: May 18, 2001Date of Patent: June 22, 2004Assignees: Infineon Technologies AG, International Business Machines CorpInventors: Youngjin Park, Heon Lee, David E. Kotecki, Greg Costrini
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Patent number: 6544832Abstract: A DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. One or more dielectric layers are deposited above the bit-lines and VIAs are formed in these layers. A sidewall is formed in the VIA above the bit-line and the VIAs are extended down to the silicon substrate and filled with a conductive material and planarized, forming the capacitor contact.Type: GrantFiled: June 18, 2001Date of Patent: April 8, 2003Assignee: International Business Machines CorporationInventors: David E. Kotecki, William H. Ma
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Publication number: 20020173094Abstract: Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.Type: ApplicationFiled: May 18, 2001Publication date: November 21, 2002Inventors: Youngjin Park, Heon Lee, David E. Kotecki, Greg Costrini
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Patent number: 6429474Abstract: A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.Type: GrantFiled: April 11, 2000Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Gary B. Bronner, David E. Kotecki, Carl J. Radens
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Patent number: 6395594Abstract: A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.Type: GrantFiled: January 2, 2001Date of Patent: May 28, 2002Assignee: International Business Machines CorporationInventors: David E. Kotecki, Carl J. Radens, Jeffrey P. Gambino, Gary B. Bronner
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Patent number: 6379577Abstract: A process and solution for selectively wet etching a titanium based perovskite material disposed on a silicon oxide or silicon nitride substrate is disclosed herein. The solution is composed of hydrogen peroxide, an acid and deionized water. The solution is heated to a temperature between 25 and 90 degrees Celsius. The titanium based perovskite material may be barium strontium titanate, barium titanate, strontium titanate or a lead titanate. The solution selectively etches the perovskite material while the substrate is only minimally etched, if at all. The process and solution allows for an etching rate up to thirty times greater than conventional etching rates for similar perovskite materials selective to various substrate, barrier and mask layers, including SiO2.Type: GrantFiled: June 10, 1999Date of Patent: April 30, 2002Assignee: International Business Machines CorporationInventors: Hiroyuki Akatsu, David E. Kotecki, Jingyu Jenny Lian, Hua Shen
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Patent number: 6355567Abstract: Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.Type: GrantFiled: June 30, 1999Date of Patent: March 12, 2002Assignee: International Business Machines CorporationInventors: Scott D. Halle, Paul C. Jamison, David E. Kotecki, Richard S. Wise
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Patent number: 6339007Abstract: A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.Type: GrantFiled: May 2, 2000Date of Patent: January 15, 2002Assignee: International Business Machines CorporationInventors: Yun-Yu Wang, Rajarao Jammy, Lee J. Kimball, David E. Kotecki, Jenny Lian, Chenting Lin, John A. Miller, Nicholas Nagel, Hua Shen, Horatio S. Wildman
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Publication number: 20010050385Abstract: A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.Type: ApplicationFiled: January 2, 2001Publication date: December 13, 2001Inventors: David E. Kotecki, Carl J. Radens, Jeffrey P. Gambino, Gary B. Bronner
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Publication number: 20010037995Abstract: A process and solution for selectively wet etching a titanium based perovskite material disposed on a silicon oxide or silicon nitride substrate is disclosed herein. The solution is composed of hydrogen peroxide, an acid and deionized water. The solution is heated to a temperature between 25 and 90 degrees Celsius. The titanium based perovskite material may be barium strontium titanate, barium titanate, strontium titanate or a lead titanate. The solution selectively etches the perovskite material while the substrate is only minimally etched, if at all. The process and solution allows for an etching rate up to thirty times greater than conventional etching rates for similar perovskite materials selective to various substrate, barrier and mask layers, including SiO2.Type: ApplicationFiled: June 10, 1999Publication date: November 8, 2001Inventors: HIROYUKI AKATSU, DAVID E. KOTECKI, JINGYU JENNY LIAN, HUA SHEN
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Publication number: 20010035551Abstract: A DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. One or more dielectric layers are deposited above the bit-lines and VIAs are formed in these layers. A sidewall is formed in the VIA above the bit-line and the VIAs are extended down to the silicon substrate and filled with a conductive material and planarized, forming the capacitor contact.Type: ApplicationFiled: June 18, 2001Publication date: November 1, 2001Inventors: David E. Kotecki, William H. Ma
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Publication number: 20010016226Abstract: This invention relates to a method for improving the chemical and electrical performance characteristics of a dielectric material especially one with high dielectric constant. The method comprises the steps of first obtaining a high dielectric constant material, the material having a degraded upper surface reduced dielectric constant and then modifying the surface chemistry of said upper surface by reacting said upper surface with a reactant. The reaction enables removal of the degraded layer. In a variant of the method, the gas reactant preferentially reacting with upper surface as compared to the bulk.Type: ApplicationFiled: April 2, 2001Publication date: August 23, 2001Applicant: International Business Machines CorporationInventors: Wesley Natzle, Peter R. Duncombe, Rajarao Jammy, David E. Kotecki, Robert B. Laibowitz, Chienfan Yu
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Patent number: 6268259Abstract: An overhanging separator structure with a post projecting from a surface which may be a substrate, an underlying layer on the surface, and a separator layer on the underlying layer, with the separator layer overhanging the underlying layer. A discontinuous film is then formed in a single process step having a first portion on the separator layer and a second portion on the post, the discontinuity caused by the overhanging separator layer. The structure is made into a stacked capacitor with the second (post) portion of the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.Type: GrantFiled: June 23, 1998Date of Patent: July 31, 2001Assignee: International Business Machines CorporationInventors: David E. Kotecki, William H. Ma
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Patent number: 6262450Abstract: A DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. One or more dielectric layers are deposited above the bit-lines and VIAs are formed in these layers. A sidewall is formed in the VIA above the bit-line and the VIAs are extended down to the silicon substrate and filled with a conductive material and planarized, forming the capacitor contact.Type: GrantFiled: April 22, 1998Date of Patent: July 17, 2001Assignee: International Business Machines CorporationInventors: David E. Kotecki, William H. Ma
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Patent number: 6255157Abstract: A structure and method for forming an integrated circuit structure including forming at least one transistor structure, forming at least one ferroelectric capacitor above the transistor structure, annealing the ferroelectric capacitor, and forming at least one conductive contact between the transistor structure and the ferroelectric capacitor.Type: GrantFiled: January 27, 1999Date of Patent: July 3, 2001Assignee: International Business Machines CorporationInventors: Louis L. Hsu, David E. Kotecki, Jack A. Mandelman
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Patent number: 6222219Abstract: A structure and process for fabricating a crown capacitor using a tapered etch and chemical mechanical polishing to form a bottom electrode having an increased area and crown is provided. The tapered etch is used to form a trough in an interlevel dielectric, e.g. SiO2, and is performed over contact hole forming a crown-like structure. The trough and, optionally, the crown are then covered by a conductor, which is patterned by chemical mechanical polishing.Type: GrantFiled: October 30, 1998Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, David E. Kotecki
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Patent number: 6207584Abstract: A method for forming a dielectric layer includes exposing a surface to a first dielectric material in gaseous form at a first temperature. Nuclei of the first dielectric material are formed on the surface. A layer of a second dielectric material is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.Type: GrantFiled: January 5, 2000Date of Patent: March 27, 2001Assignees: International Business Machines Corp., Infineon Technologies North America Corp.Inventors: Hua Shen, David E. Kotecki, Robert Laibowitz, Katherine Lynn Saenger, Satish D. Athavale, Jenny Lian, Martin Gutsche, Yun-Yu Wang, Thomas Shaw
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Patent number: 6201272Abstract: A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.Type: GrantFiled: April 28, 1999Date of Patent: March 13, 2001Assignee: International Business Machines CorporationInventors: David E. Kotecki, Carl J. Radens, Jeffrey P. Gambino, Gary B. Bronner
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Patent number: 6191469Abstract: A discontinuous film structure on a surface which may be a substrate, with an underlying layer on the surface having a first opening formed therein, a separator layer on the underlying layer having a second opening formed therein, and the second opening overlying the first opening such that the separator layer overhangs the underlying layer. A discontinuous-as-deposited film is formed on the separator layer, with the discontinuity substantially in register with the second opening. The structure is made into a stacked capacitor with the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.Type: GrantFiled: March 21, 2000Date of Patent: February 20, 2001Assignee: International Business Machines CorporationInventors: David E. Kotecki, William H. Ma
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Patent number: 6178082Abstract: A multilayer ceramic substrate having a thin film structure containing capacitor connected thereto is provided as an interposer capacitor, the capacitor employing platinum as the bottom electrode of the capacitor. In a preferred capacitor, a dielectric material such as barium titanate is used as the dielectric material between the capacitor electrodes. The fabrication of the interposer capacitor requires an in-situ or post deposition high temperature anneal and the use of such dielectrics requires heating of the capacitor structure in a non-reducing atmosphere. A layer of a high temperature, thin film diffusion barrier such as TaSiN on the lower platinum electrode between the electrode and underlying multilayer ceramic substrate prevents or minimizes oxidization of the metallization of the multilayer ceramic substrate to which the thin film structure is connected during the fabrication process.Type: GrantFiled: February 26, 1998Date of Patent: January 23, 2001Assignee: International Business Machines CorporationInventors: Mukta S. Farooq, David E. Kotecki, Robert A. Rita, Stephen M. Rossnagel