Abstract: An integrated circuit including a capacitor and a method of manufacturing the capacitor simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings corresponding to vias and capacitors extend through a second interlevel dielectric to the first interconnect layer. A conductor is deposited in the via openings. An insulator is deposited in the openings and on the conductor in the via openings. A trench is then etched into the upper portion of the via openings while simultaneously removing the insulator from the conductor in the via openings. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

Abstract: A discontinuous film structure on a surface which may be a substrate, with an underlying layer on the surface having a first opening formed therein, a separator layer on the underlying layer having a second opening formed therein, and the second opening overlying the first opening such that the separator layer overhangs the underlying layer. A discontinuous-as-deposited film is formed on the separator layer, with the discontinuity substantially in register with the second opening. The structure is made into a stacked capacitor with the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Abstract: A discontinuous film structure on a substrate, with an etch stop layer on the substrate, a separator layer with an opening formed therein on the etch stop layer and a discontinuous-as-deposited film on the separator layer, the discontinuity substantially in register with the opening. The structure is made into a stacked capacitor with the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Abstract: A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.

Abstract: This invention relates to a method for improving the chemical and electrical performance characteristics of a high dielectric constant material. The method comprises the steps of first obtaining a barium containing high dielectric constant material, the material having an upper surface and then modifying the surface chemistry of said upper surface by interacting said upper surface with a gas reactant in a closed environment. In a variant of the method, the gas reactant preferentially reacting with upper surface as compared to the bulk.

Abstract: An integrated circuit including a capacitor and a method of manufacturing the capacitor simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings corresponding to vias and capacitors extend through a second interlevel dielectric to the first interconnect layer. A conductor is deposited in the via openings. An insulator is deposited in the openings and on the conductor in the via openings. A trench is then etched into the upper portion of the via openings while simultaneously removing the insulator from the conductor in the via openings. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

Abstract: A showerhead disperser device for mixing plural vapor streams, comprising: a housing including front and rear walls in spaced apart relation to one another, and a side wall therebetween, defining within the housing an interior volume; the front wall having a multiplicity of vapor mixture discharge openings therein, for discharging mixed vapor from the interior volume of the housing exteriorly thereof, flow passages joined to the housing for introducing into the interior volume of the housing respective fluids to be mixed therein; and at least one baffle plate mounted in the interior volume of the housing, intermediate the front and rear walls of the housing, the baffle plate having an edge in spaced relation to the side wall to form an annular flow passage therebetween and the baffle plate having at least one of the respective fluids directed thereagainst upon introduction to the interior volume of the housing, for distribution thereof in the interior volume of the housing.

Abstract: An adherent separator structure with a post projecting from a surface which may be a substrate, and a separator adhering to the post, the separator spaced a distance above the surface. A discontinuous film is then formed in a single process step having a first portion on the substrate and a second portion on the post, the discontinuity proximate to and caused by the separator. The structure is made into a stacked capacitor with the second (post) portion of the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Abstract: A semiconductor device having a capacitor containing an insulator material having a high dielectric constant and high charge storing capability of the following formula: (A.sup.1).sub.x (A.sup.2).sub.2-x (D).sub.d (B.sup.1).sub.y (B.sup.2).sub.1-y O.sub.4 where A.sup.1 and A.sup.2 are cations, B.sup.1 and B.sup.2 are anions, 0.ltoreq.x.ltoreq.2 with the proviso that A.sup.1 and A.sup.2 are different types of atoms when 0<x<2, and 0.ltoreq.y.ltoreq.1 with the proviso that B.sup.1 and B.sup.2 are different types of atoms when 0<y<1, and D is an optional dopant in a total amount of 0.ltoreq.d.ltoreq.0.1.

Abstract: A discontinuous film structure on a substrate, with an etch stop layer on the substrate, a separator layer with an opening formed therein on the etch stop layer and a discontinuous-as-deposited film on the separator layer, the discontinuity substantially in register with the opening. The structure is made into a stacked capacitor with the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Abstract: A structure and process for fabricating a crown capacitor using a tapered etch and chemical mechanical polishing to form a bottom electrode having an increased area and crown is provided. The tapered etch is used to form a trough in an interlevel dielectric, e.g. SiO.sub.2, and is performed over contact hole forming a crown-like structure. The trough and, optionally, the crown are then covered by a conductor, which is patterned by chemical mechanical polishing.

Abstract: An overhanging separator structure with a post projecting from a surface which may be a substrate, an underlying layer on the surface, and a separator layer on the underlying layer, with the separator layer overhanging the underlying layer. A discontinuous film is then formed in a single process step having a first portion on the separator layer and a second portion on the post, the discontinuity caused by the overhanging separator layer. The structure is made into a stacked capacitor with the second (post) portion of the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Abstract: A showerhead disperser device for mixing plural vapor streams, comprising: a housing including front and rear walls in spaced apart relation to one another, and a side wall therebetween, defining within the housing an interior volume; the front wall having a multiplicity of vapor mixture discharge openings therein, for discharging mixed vapor from the interior volume of the housing exteriorly thereof, flow passages joined to the housing for introducing into the interior volume of the housing respective fluids to be mixed therein; and at least one baffle plate mounted in the interior volume of the housing, intermediate the front and rear walls of the housing, the baffle plate having an edge in spaced relation to the side wall to form an annular flow passage therebetween and the baffle plate having at least one of the respective fluids directed thereagainst upon introduction to the interior volume of the housing, for distribution thereof in the interior volume of the housing.

Abstract: A reactor is provided for heating a workpiece in a sealed environment. The reactor has a chamber with a gas inlet port, a gas outlet port, and at least one tube for receiving a heat source. The tube passes from outside the chamber into the inside of the chamber without breaking the chamber seal. Alternately, the tubes may be used for treating the workpiece with light, in combination with or instead of heat treatment.

Abstract: A capacitor structure is provided, with a first conductor on top of a substrate having at least one layer of dielectric material thereon; a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein; a second conductor, in electrical contact with the first conductor, formed on the sidewalls of the first opening; a non-conductive sidewall spacer formed in the first opening and contacting the second conductor, the non-conductive sidewall spacer having a second opening formed therein; and a third conductor formed in the second opening.

Abstract: An isolated sidewall capacitor with dual dielectric, which includes two capacitors. The first capacitor includes a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening. The second capacitor includes the second conductor, a first non-conductor disposed over the top portion of the second conductor, a third conductor disposed over the first non-conductor, and the third conductor electrically connected to the first conductor. A second non-conductor isolates the first conductor from the second conductor.

Abstract: An electrostatic chuck (ESC) provides increased temperature uniformity and adjustment capability of the surface of a wafer or wafer-like workpiece during processing, for example, in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor. Temperature uniformity is achieved through an improved pattern of grooves in the face of the ESC which allows an inert gas to be contained between the ESC and a wafer held thereby even at high levels of vacuum. The ESC is adapted for a particular desired temperature range by choice of surface roughness of the remaining areas of the face of the ESC. Adjustability within that range is achieved by variation of the electrostatic voltage by which a wafer is held against the chuck face.

Abstract: A removable gas injector design compatible for use in chemical vapor deposition reactors that allows proper mixing of the reactant gases, reduced cycle time associated with cleaning of gas injector components, and elimination of uncertainties associated with manual cleaning of the injector. A better reliability to the system due to the known condition of the nozzle after a clean is achieved.

Abstract: A polyemitter structure having a thin interfacial layer deposited between the polysilicon emitter contact and the crystalline silicon emitter, as opposed to a regrown SiO.sub.x layer, has improved reproducibility and performance characteristics. A n-doped hydrogenated microcrystalline silicon film can be used as the deposited interfacial film between a crystalline silicon emitter and a polycrystalline silicon contact.

Abstract: A heat dissipation apparatus for dissipation of thermal energy from an isolated active silicon region to an underlying supportive substrate is disclosed. Such an apparatus comprises a diamond filled trench having walls extending through the isolated active silicon region, an underlying insulative layer, and into the supportive substrate, whereby said diamond filled trench provides a high thermal conductive path from said active silicon region to said substrate.