Patents by Inventor David E. Kruse

David E. Kruse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8841963
    Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: September 23, 2014
    Assignee: Broadcom Corporation
    Inventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Bag
    Publication number: 20130320054
    Abstract: A bag or pack for transporting material, which may include air tank bottles, rope, and/or other firefighting gear. The bag may be used in multiple different ways, but may be especially configured to rest on top of a primary air tank worn by the user and to avoid falling between that tank and the user's back. Pockets in the bag may allow the user to install bottles in an upright or inverted configuration, which may aid the user in quickly determining which bottles are usable. Bag may free up the user's hands, allowing him to carry extra gear and requiring further trips from a supply source to a staging area, which may be several floors up, e.g., in the case of a high rise environment.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 5, 2013
    Inventor: David E. Kruse
  • Patent number: 8451885
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: May 28, 2013
    Assignee: Broadcom Corporation
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 8306104
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: November 6, 2012
    Assignee: Broadcom Corporation
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 8031799
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: October 4, 2011
    Assignee: Broadcom Corporation
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Publication number: 20110096824
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Application
    Filed: September 7, 2010
    Publication date: April 28, 2011
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Publication number: 20110064123
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Application
    Filed: August 3, 2010
    Publication date: March 17, 2011
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Publication number: 20100309963
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 9, 2010
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 7801241
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: September 21, 2010
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 7801240
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: September 21, 2010
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 7792186
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: September 7, 2010
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 7769101
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: August 3, 2010
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 7733952
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: June 8, 2010
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 7671681
    Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: March 2, 2010
    Inventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Publication number: 20090296791
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Application
    Filed: August 3, 2009
    Publication date: December 3, 2009
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 7598808
    Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: October 6, 2009
    Inventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 7570701
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: August 4, 2009
    Assignee: Broadcom Corporation
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Publication number: 20090180529
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Application
    Filed: November 18, 2008
    Publication date: July 16, 2009
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Patent number: 7453935
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: November 18, 2008
    Assignee: Broadcom Corporation
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
  • Publication number: 20080151988
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 26, 2008
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli