Patents by Inventor David E. Kruse
David E. Kruse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080150632Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: ApplicationFiled: February 26, 2008Publication date: June 26, 2008Inventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7336131Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: GrantFiled: May 25, 2006Date of Patent: February 26, 2008Assignee: Broadcom CorporationInventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7305029Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: October 8, 2003Date of Patent: December 4, 2007Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7263134Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: August 17, 2004Date of Patent: August 28, 2007Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, Henry Samueli, David E. Kruse, Arthur Abnous
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Patent number: 7197069Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: October 8, 2003Date of Patent: March 27, 2007Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7194029Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: October 8, 2003Date of Patent: March 20, 2007Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7194028Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: October 8, 2003Date of Patent: March 20, 2007Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, Henry Samueli, David E. Kruse, Arthur Abnous
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Patent number: 7148750Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: GrantFiled: May 2, 2006Date of Patent: December 12, 2006Assignee: Broadcom CorporationInventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7053715Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: GrantFiled: December 6, 2004Date of Patent: May 30, 2006Assignee: Broadcom CorporationInventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7038545Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: GrantFiled: October 28, 2003Date of Patent: May 2, 2006Assignee: Broadcom CorporationInventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 7038533Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: GrantFiled: October 28, 2003Date of Patent: May 2, 2006Assignee: Broadcom CorporationInventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 6828860Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: GrantFiled: October 28, 2003Date of Patent: December 7, 2004Assignee: Broadcom CorporationInventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 6798283Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: GrantFiled: October 28, 2003Date of Patent: September 28, 2004Assignee: Broadcom CorporationInventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 6778602Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: February 28, 2002Date of Patent: August 17, 2004Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, Henry Samueli, David E. Kruse, Arthur Abnous
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Publication number: 20040156461Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: ApplicationFiled: October 8, 2003Publication date: August 12, 2004Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Patent number: 6771725Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: GrantFiled: July 29, 2002Date of Patent: August 3, 2004Assignee: Broadcom CorporationInventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Publication number: 20040108892Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: ApplicationFiled: October 28, 2003Publication date: June 10, 2004Inventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Publication number: 20040091038Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.Type: ApplicationFiled: October 8, 2003Publication date: May 13, 2004Inventors: Oacar E. Agazzi, John L. Creigh, Mehdi Hatamlan, David E. Kruse, Arthur Abnous, Henry Samueli
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Publication number: 20040085128Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: ApplicationFiled: October 28, 2003Publication date: May 6, 2004Inventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli
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Publication number: 20040085125Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.Type: ApplicationFiled: October 28, 2003Publication date: May 6, 2004Inventors: Arya R. Behzad, Klaas Bult, Ramon A. Gomez, Chi-Hung Lin, Tom W. Kwan, Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, David E. Kruse, Arthur Abnous, Henry Samueli