Patents by Inventor David E. Lackey
David E. Lackey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8589843Abstract: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.Type: GrantFiled: January 20, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: David E. Lackey, Chandramouili Visweswariah, Paul S. Zuchowski
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Patent number: 8543966Abstract: A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.Type: GrantFiled: November 11, 2011Date of Patent: September 24, 2013Assignee: International Business Machines CorporationInventors: Jeanne P. Bickford, Peter A. Habitz, Vikram Iyengar, David E. Lackey, Jinjun Xiong
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Patent number: 8504971Abstract: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.Type: GrantFiled: January 20, 2012Date of Patent: August 6, 2013Assignee: International Business Machines CorporationInventors: David E. Lackey, Chandramouili Visweswariah, Paul S. Zuchowski
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Patent number: 8490045Abstract: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.Type: GrantFiled: January 20, 2012Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: David E. Lackey, Chandramouili Visweswariah, Paul S. Zuchowski
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Patent number: 8490040Abstract: A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.Type: GrantFiled: November 11, 2011Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Jeanne P. Bickford, Peter A. Habitz, Vikram Iyengar, David E. Lackey, Jinjun Xiong
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Publication number: 20130125073Abstract: A method of test path selection and test program generation for performance testing integrated circuits.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeanne P. Bickford, Peter A. Habitz, Vikram Iyengar, David E. Lackey, Jinjun Xiong
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Publication number: 20130125076Abstract: A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeanne P. Bickford, Peter A. Habitz, Vikram Iyengar, David E. Lackey, Jinjun Xiong
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Patent number: 8423844Abstract: A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.Type: GrantFiled: January 11, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Pamela S. Gillis, David E. Lackey, Steven F. Oakland, Jeffery H. Oppold
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Patent number: 8423847Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.Type: GrantFiled: May 11, 2012Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Gary D. Grise, David E. Lackey, Steven F. Oakland, Donald L. Wheater
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Publication number: 20120221910Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.Type: ApplicationFiled: May 11, 2012Publication date: August 30, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary D. GRISE, David E. LACKEY, Steven F. OAKLAND, Donald L. Wheater
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Patent number: 8239715Abstract: A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.Type: GrantFiled: June 24, 2008Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Steven M. Eustis, Kevin W. Gorman, David E. Lackey, Michael R. Ouellette
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Publication number: 20120179944Abstract: A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.Type: ApplicationFiled: January 11, 2011Publication date: July 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pamela S. Gillis, David E. Lackey, Steven F. Oakland, Jeffery H. Oppold
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Patent number: 8205124Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.Type: GrantFiled: November 11, 2008Date of Patent: June 19, 2012Assignee: International Business Machines CorporationInventors: Gary D. Grise, David E. Lackey, Steven F. Oakland, Donald L. Wheater
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Publication number: 20120124538Abstract: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.Type: ApplicationFiled: January 20, 2012Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David E. LACKEY, Chandramouili VISWESWARIAH, Paul S. ZUCHOWSKI
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Patent number: 8181135Abstract: A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.Type: GrantFiled: August 27, 2009Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Vikram Iyengar, Pamela S. Gillis, David E. Lackey, Steven F. Oakland
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Publication number: 20120112341Abstract: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.Type: ApplicationFiled: January 20, 2012Publication date: May 10, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David E. LACKEY, Chandramouili VISWESWARIAH, Paul S. ZUCHOWSKI
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Publication number: 20120115256Abstract: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.Type: ApplicationFiled: January 20, 2012Publication date: May 10, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David E. LACKEY, Chandramouili VISWESWARIAH, Paul S. ZUCHOWSKI
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Patent number: 8122409Abstract: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.Type: GrantFiled: October 9, 2007Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: David E. Lackey, Chandramouli Visweswariah, Paul S. Zuchowski
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Patent number: 8117579Abstract: A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.Type: GrantFiled: January 31, 2008Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: James Douglas Warnock, Wendel Dieter, David E. Lackey, William Vincent Huott, Leon Jacob Sigal, Louis Bernard Bushard, Sang Hoo Dhong
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Patent number: 7996807Abstract: Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations.Type: GrantFiled: April 17, 2008Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Gary D. Grise, Vikram Iyengar, David E. Lackey, David W. Milton