Abstract: A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.

Abstract: A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.

Abstract: A method of testing a digital logic circuit comprises first providing a logic circuit having a plurality of interconnected circuits each having an input and an output; determining a gate level representation of the logic circuit including test nets for determining faults in the circuit; and identifying a portion of the nets which are most difficult to test, including nets which are most difficult to control and nets which are most difficult to observe. The method then includes inserting into the logic circuit control latches for nets which are determined to be most difficult to control and inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe. Using the inserted control latches and observation latches, the method further includes testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit.

Abstract: A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.

Abstract: A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

Abstract: An apparatus for assisting backside focused ion beam (FIB) device modification is disclosed. The apparatus for assisting backside FIB device modification includes an FIB device modification circuit and a control circuit. The FIB device modification circuit includes an input, an output, an FIB input pad, and an FIB output pad. The FIB device modification circuit allows the input to be electrically connected to the output. The control circuit, which is coupled to the FIB device modification circuit, may include a jumper and a cut. The control circuit is preferably located in a proximity of a backside of a substrate to allow the jumper and the cut to be modified by an FIB machine.

Abstract: An apparatus for assisting backside focused ion beam (FIB) device modification is disclosed. The apparatus for assisting backside FIB device modification includes an FIB device modification circuit and a control circuit. The FIB device modification circuit includes an input, an output, an FIB input pad, and an FIB output pad. The FIB device modification circuit allows the input to be electrically connected to the output. The control circuit, which is coupled to the FIB device modification circuit, may include a jumper and a cut. The control circuit is preferably located in a proximity of a backside of a substrate to allow the jumper and the cut to be modified by an FIB machine.

Abstract: An integrated circuit employing a built-in self testing is provided. The circuit comprises a clock controller, a plurality of logic domains, and a system clock. The clock controller includes a plurality of programmable clock templates. The logic domains operate based on clocks having different clocks and/or on different edges of the clocks and operable asynchronously with respect to the others of said logic domains. The system clock is distributed to the logic domains and to the clock controller. Herein, each logic domain generates master/slave signals in response to the received system clock and each of the clock templates distributes enabling signals to at least one corresponding logic domain. The enabling signals are for selectively gating the generated master/slave signals for distribution throughout at least one corresponding logic domain.

Abstract: METHOD FOR TESTING INTEGRATED LOGIC CIRCUITS A method of testing a circuit having multiple elements is disclosed. A plurality of faults representing the elements of the circuit for testing said circuit is created. The faults are grouped based on common attributes of the faults. A test pattern for each group of faults is created. Finally, the circuit is tested using test patterns for each group of faults.

Abstract: A method of inserting test points in a circuit design includes selecting a node in the circuit design, determining a driver cell of the node, selecting a replacement cell for the driver cell and replacing the driver cell in the circuit design with the replacement cell. The replacement cell has the same function of the driver cell as well as a test point function. Additionally, the replacement cell is chosen so as not to break timing.

Abstract: A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

Abstract: An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.

Abstract: A remote clock signal generation means is provided which allows a plurality of clock signals to be generated remotely at the "leaf" level thereby removing the need to have multiple clock signals at the system, or "tree" level. More particularly, this system is designed for use in an LBIST circuit featuring LSSD master-slave clock control. This disclosure teaches a clock control method and structure in which the master and slave clocks are generated directly from the system clock after the clock powering logic to thereby avoid intrusion or modification effects associated with logical manipulation of the clock signals.

Abstract: Software simulators of logic design circuits run slowly but are capable of providing very finely detailed error trace analyses. On the other hand, hardware accelerators operating to perform similar functions are very fast in their execution but are not capable of practically isolating error states or other critical conditions. Accordingly, the present invention provides an interactive system combining software simulators and hardware accelerators so that when desired test results do not favorably compare with simulated results, a mechanism is provided for storing the current hardware accelerator state and restoring the accelerator to a previous checkpoint state which has been saved as a result of a prior periodic interruption. The hardware accelerator is then operated for a time sufficient to bring it up to a state that occurs just before the detected miscomparison. At this point, state information from the hardware accelerator is supplied to a software simulator for detailed error analysis and fault tracing.