Abstract: Embodiments of the invention contemplate the formation of a low cost flexible solar cell using a novel electroplating method and apparatus to form a metal contact structure. The apparatus and methods described herein remove the need to perform one or more high temperature screen printing processes to form conductive features on the surface of a solar cell substrate. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. Solar cell substrates that may benefit from the invention include flexible substrates may have an active region that contains organic material, single crystal silicon, multi-crystalline silicon, polycrystalline silicon, germanium, and gallium arsenide, cadmium telluride, cadmium sulfide, copper indium gallium selenide, copper indium selenide, gallilium indium phosphide, as well as heterojunction cells that are used to convert sunlight to electrical power.

Abstract: A metal contact structure of a solar cell substrate includes a contact with a conductive layer or a capping layer that is formed using an electroless plating process. The contact may be disposed within a hole formed through the solar cell substrate or on a non-light-receiving surface of the solar cell substrate. The electroless plating process for the conductive layer uses a seed layer that includes an activation layer for electroless plating.

Abstract: Embodiments of the invention contemplate the formation of a low cost solar cell metal contact structure that has improved electrical and mechanical properties through the use of an electrochemical plating process. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connections that is reliable and cost effective. One or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing common metal, such as copper. However, generally the electroplated portions of the interconnecting layer may contain a substantially pure metal or a metal alloy layer. Methods are discussed herein that are used to form a solar cell containing conductive metal interconnect layer(s) that have a low intrinsic stress.

Abstract: A method of suppressing parasitic particle formation in a metal organic chemical vapor deposition process is described. The method may include providing a substrate to a reaction chamber, and introducing an organometallic precursor, a particle suppression compound and at least a second precursor to the reaction chamber. The second precursor reacts with the organometallic precursor to form a nucleation layer on the substrate. Also, a method of suppressing parasitic particle formation during formation of a III-V nitride layer is described. The method includes introducing a group III metal containing precursor to a reaction chamber. The group III metal precursor may include a halogen. A hydrogen halide gas and a nitrogen containing gas are also introduced to the reaction chamber. The nitrogen containing gas reacts with the group III metal precursor to form the Ill-V nitride layer on the substrate.

Abstract: Methods and systems permit fabricating structures using liquid sources without active temperature control. A liquid or solid source of the precursor is provided in a bubbler. A carrier gas source is flowed into the source to generate a flow of precursor vapor carried by the carrier gas. A relative concentration of the precursor vapor to the carrier gas of the flow is measured. A mass flow rate of the precursor in the flow is determined from the measured relative concentration. A flow rate of the carrier gas into the source is changed to maintain the mass flow rate at a defined value or within a defined range.

Abstract: Methods and systems permit fabricating structures using liquid sources without active temperature control. A substrate is disposed within a substrate processing chamber. A liquid source of a group-III precursor is provided in a bubbler. A push gas is applied to the liquid source to drive the group-III precursor into a vaporizer. A carrier gas is flowed into the vaporizer. A flow of vaporized group-III precursor carried by the carrier gas is injected from the vaporizer into the processing chamber. A nitrogen precursor is flowed into the processing chamber. A group-III nitride layer is deposited over the substrate with a thermal chemical vapor deposition within the processing chamber using the vaporized group-III precursor and the nitrogen precursor.

Abstract: A compound nitride semiconductor substrate includes a substrate having a first side and a second side. A first layer overlies the first side of the substrate and a second layer overlies the second side of the substrate. The first layer includes a first group-III element and nitrogen. The second layer includes a second group-III element and nitrogen.

Abstract: Apparatus and methods are described for fabricating a compound nitride semiconductor structure. Group-III and nitrogen precursors are flowed into a first processing chamber to deposit a first layer over a substrate with a thermal chemical-vapor-deposition process. The substrate is transferred from the first processing chamber to a second processing chamber. Group-III and nitrogen precursors are flowed into the second processing chamber to deposit a second layer over the first layer with a thermal chemical-vapor-deposition process. The first and second group-III precursors have different group-III elements.

Abstract: Methods are provided of fabricating a nitride semiconductor structure. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over one side of the substrate with a thermal chemical-vapor-deposition process. A second layer is similarly deposited over an opposite side of the substrate using the group-III precursor and the nitrogen precursor. The substrate is cooled after depositing the first and second layers without substantially deforming a shape of the substrate.

Abstract: Methods are provided of fabricating compound nitride semiconductor structures. A group-III precursor and a nitrogen precursor are flowed into a processing chamber to deposit a first layer over a surface of a first substrate with a thermal chemical-vapor-deposition process. A second layer is deposited over a surface of a second substrate with the thermal chemical-vapor-deposition process using the first group-III precursor and the first nitrogen precursor. The first and second substrates are different outer substrates of a plurality of stacked substrates disposed within the processing chamber as a stack so that the first and second layers are deposited on opposite sides of the stack. Deposition of the first layer and deposition of the second layer are performed simultaneously.

Abstract: Processing steps that are useful for forming interconnects in a photovoltaic module are described herein. According to one aspect, a method according to the invention includes processing steps that are similar to those performed in conventional integrated circuit fabrication. For example, the method can include etches to form a conductive step adjacent to the grooves that can be used to form interconnects between cells. According to another aspect the method for forming the conductive step can be self-aligned, such as by positioning a mirror above the module and exposing photoresist from underneath the substrate at an angle one or more times, and etching to expose the conductive step.

Abstract: In a module of photovoltaic cells, a method of forming the module interconnects includes a single cutting process after the deposition of all active layers. This simplifies the overall process to a set of vacuum steps followed by a set of interconnect steps, and may significantly module quality and yield. According to another aspect, an interconnect forming method includes self-aligned deposition of an insulator. This simplifies the process because no alignment is required. According to another aspect, an interconnect forming method includes a scribing process that results in a much narrower interconnect which may significantly boost cell efficiency, and allow for narrower cell sizes. According to another aspect, an interconnect includes an insulator layer that greatly reduces shunt current through the active layer, which can greatly improve cell efficiency.

Abstract: Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.