Patents by Inventor David Edward Fisch
David Edward Fisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190252375Abstract: A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the front surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors.Type: ApplicationFiled: February 9, 2018Publication date: August 15, 2019Inventors: Javier A. DELACRUZ, David Edward FISCH, Kenneth DUONG, Xu CHANG, Liang WANG
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Patent number: 10262717Abstract: The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.Type: GrantFiled: November 3, 2017Date of Patent: April 16, 2019Assignee: Invensas CorporationInventors: David Edward Fisch, William C. Plants
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Patent number: 10164633Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.Type: GrantFiled: July 10, 2017Date of Patent: December 25, 2018Assignee: Invensas CorporationInventors: Curtis Dicke, George Courville, David Edward Fisch, Randall Sandusky, Kent Stalnaker
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Publication number: 20180173600Abstract: This disclosure pertains to hardware compute arrays (sometimes called systolic arrays) for applications such as artificial intelligence (AI), machine learning (ML), digital signal processing (DSP), graphics processing units (GPUs), and other computationally intensive applications. More particularly, it pertains to novel and advantageous architecture innovations for efficiently and inexpensively implementing such arrays using multiple integrated circuits. Hardware and methods are disclosed to allow compute arrays to be tested after face-to-face or wafer-to-wafer bonding and without out any pre-bonding test. Defects discovered in the post-bonding testing can be completely or partially healed increasing yields and reducing costs.Type: ApplicationFiled: December 20, 2017Publication date: June 21, 2018Inventors: Javier A. DELACRUZ, Steven L. TEIG, David Edward FISCH, William C. PLANTS
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Publication number: 20180114561Abstract: The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.Type: ApplicationFiled: November 3, 2017Publication date: April 26, 2018Applicant: Invensas CorporationInventors: David Edward Fisch, William C. Plants
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Publication number: 20180102251Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates.Type: ApplicationFiled: October 4, 2017Publication date: April 12, 2018Inventors: Javier A. DELACRUZ, Steven L. TEIG, Shaowu HUANG, William C. PLANTS, David Edward FISCH
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Patent number: 9812185Abstract: The invention pertains to data disturb vulnerabilities in Dynamic Random Access Memory (DRAM) integrated circuits. In particular, it pertains to mitigating attacks on a computational system by deliberate inducement of disturbs on a targeted row (also known as “row hammering”) in the system's DRAM memory. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate. When a tracked address poses a danger of causing a memory disturb, each row adjacent to the tracked address row is refreshed thus mitigating the danger.Type: GrantFiled: February 9, 2016Date of Patent: November 7, 2017Assignee: Invensas CorporationInventors: David Edward Fisch, William C. Plants
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Publication number: 20170310322Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.Type: ApplicationFiled: July 10, 2017Publication date: October 26, 2017Applicant: Invensas CorporationInventors: Curtis Dicke, George Courville, David Edward Fisch, Randall Sandusky, Kent Stalnaker
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Publication number: 20170207141Abstract: System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having a top surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation.Type: ApplicationFiled: April 3, 2017Publication date: July 20, 2017Inventor: David Edward Fisch
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Publication number: 20170117030Abstract: The invention pertains to mitigation of row hammer attacks in DRAM integrated circuits. Apparatus and methods are disclosed for an embedded target row refresh (TRR) solution with modest overhead. In operation it is nearly transparent to the user. Except for enablement via the mode register and an increase in the average refresh rate on the order of half of one percent, no further user action is required. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate.Type: ApplicationFiled: February 9, 2016Publication date: April 27, 2017Applicant: Invensas CorporationInventors: David Edward Fisch, William C. Plants
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Patent number: 9620433Abstract: System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having atop surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation.Type: GrantFiled: December 31, 2013Date of Patent: April 11, 2017Assignee: Tessera, Inc.Inventor: David Edward Fisch
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Patent number: 9548101Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: GrantFiled: March 9, 2016Date of Patent: January 17, 2017Assignee: Invensas CorporationInventors: David Edward Fisch, William C. Plants, Kent Stalnaker
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Publication number: 20160189765Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: ApplicationFiled: March 9, 2016Publication date: June 30, 2016Applicant: Invensas CorporationInventors: David Edward Fisch, William C. Plants, Kent Stalnaker
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Patent number: 9299398Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: GrantFiled: April 10, 2015Date of Patent: March 29, 2016Assignee: Invensas CorporationInventors: David Edward Fisch, William C. Plants, Kent Stalnaker
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Patent number: 9230814Abstract: Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.Type: GrantFiled: October 28, 2011Date of Patent: January 5, 2016Assignee: INVENSAS CORPORATIONInventors: David Edward Fisch, Michael Curtis Parris
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Publication number: 20150213847Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: ApplicationFiled: April 10, 2015Publication date: July 30, 2015Applicant: INVENSAS CORPORATIONInventors: David Edward Fisch, William C. Plants, Kent Stalnaker
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Patent number: 9007866Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: GrantFiled: April 23, 2013Date of Patent: April 14, 2015Assignee: Tessera Inc.Inventors: David Edward Fisch, William C. Plants, Kent Stalnaker
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Patent number: 8873302Abstract: An array of memory cells, in which one or more memory cells have a common doped region. Each memory cell includes a transistor with a floating gate, source and drain regions, and separate gate and drain voltage controls. Each memory cell also includes a coupling capacitor electrically coupled to and located laterally from the floating gate. In the array, first bit lines are oriented in a first direction, wherein a first bit line is coupled to drain regions of transistors that are arranged in a column. The array includes second bit lines also oriented in the first direction, wherein a second bit line is coupled to source regions of transistors that are arranged in a column. The array also includes word lines oriented in a second direction, wherein each word line is coupled to control gates of coupling capacitors that are arranged in a row.Type: GrantFiled: October 28, 2011Date of Patent: October 28, 2014Assignee: Invensas CorporationInventors: David Edward Fisch, William C. Plants, Michael Curtis Parris
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Publication number: 20140175647Abstract: System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having atop surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation.Type: ApplicationFiled: December 31, 2013Publication date: June 26, 2014Applicant: Tessera Inc.Inventor: David Edward Fisch
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Patent number: 8618647Abstract: System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having a top surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation.Type: GrantFiled: August 1, 2011Date of Patent: December 31, 2013Assignee: Tessera, Inc.Inventor: David Edward Fisch