Abstract: An array of memory cells, in which one or more memory cells have a common doped region. Each memory cell includes a transistor with a floating gate, source and drain regions, and separate gate and drain voltage controls. Each memory cell also includes a coupling capacitor electrically coupled to and located laterally from the floating gate. In the array, first bit lines are oriented in a first direction, wherein a first bit line is coupled to drain regions of transistors that are arranged in a column. The array includes second bit lines also oriented in the first direction, wherein a second bit line is coupled to source regions of transistors that are arranged in a column. The array also includes word lines oriented in a second direction, wherein each word line is coupled to control gates of coupling capacitors that are arranged in a row.

Abstract: Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.

Abstract: System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having a top surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation.

Abstract: Techniques for reducing impact of array disturbs in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for reducing impact of array disturbs in a semiconductor memory device by increasing the refresh rate to the semiconductor memory device based at least in part on a frequency of active operations. The method may comprise receiving a first refresh command including a first subarray address to perform a first refresh operation to a first logical subarray of memory cells associated with the first subarray address. The method may also comprise receiving a second refresh command including a second subarray address to perform a second refresh operation to a second logical subarray of memory cells associated with the second subarray address, wherein the second refresh command is received after a time period from the reception of the first refresh command.

Abstract: Techniques for reducing impact of array disturbs in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for reducing impact of array disturbs in a semiconductor memory device by increasing the refresh rate to the semiconductor memory device based at least in part on a frequency of active operations. The method may comprise receiving a first refresh command including a first subarray address to perform a first refresh operation to a first logical subarray of memory cells associated with the first subarray address. The method may also comprise receiving a second refresh command including a second subarray address to perform a second refresh operation to a second logical subarray of memory cells associated with the second subarray address, wherein the second refresh command is received after a time period from the reception of the first refresh command.