Patents by Inventor David Erickson

David Erickson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10732931
    Abstract: A negative-operand compatible subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes two sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of two sets of scaled capacitors electrically connected to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground. A control circuit of the subtractor is configured to, in conjunction with the reset circuit, draw the difference output node to a reset voltage.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Phil Paone, David Paulsen, George Paulik, John E. Sheets, II, Karl Erickson, Gregory J. Uhlmann
  • Publication number: 20200231352
    Abstract: A barrier spout is comprised of a straw and a sealboat. The straw comprises a body having a first straw portion and a second straw portion, with an upper opening of the straw at a first end of the first straw portion and a lower opening of the straw at a second end of the second straw portion, the first straw portion and the second straw portion meeting at a second end of the first straw portion and a first end of the second straw portion. The straw is comprised of a barrier material to minimize at least one of oxygen and vapor transmission through the barrier material. The sealboat comprises a sealing material, the sealboat contacting an inner surface of the sealboat forming a liquid seal between the straw and the sealboat.
    Type: Application
    Filed: December 2, 2019
    Publication date: July 23, 2020
    Inventors: Kyle Erickson, David Bellmore, Paul Van Den Hoonaard
  • Publication number: 20200225860
    Abstract: A method and apparatus that provides a solid state drive that analyzes connection performance during I/O operations and is configured to independently modify connection performance based upon user specified input parameters without the need for host computer management.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventors: Darin Edward GERHART, Nicholas Edward ORTMEIER, Mark David ERICKSON
  • Patent number: 10713676
    Abstract: An embodiment of the invention provides a system that enables financial services companies to manage and track information about a sales force. The system includes components for managing distributors information, for validating and tracking licenses and credentials, for creating customized contracts, and for maintaining compensation structures. The system allows for configuring compensations, providing financial services companies a toolkit for creating and modeling their complex commission schedules used to compensate their sales force. The system also provides modeling tools for agreements and contracts between a financial services company or provider and the distributors who sell products. The system has a multi-component architecture comprising multiple modules, multiple data processing engines, a backbone and multiple data sources. The processing modules carry out information processing using one or more data processing engines.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 14, 2020
    Assignee: VERSATA DEVELOPMENT GROUP, INC.
    Inventors: David Chao, Brian Blount, Charles Erickson, Shari Gharavy, Cheng Zhou, Joshua Toub
  • Publication number: 20200217795
    Abstract: A method of distinguishing between proteinaceous and non-proteinaceous particulates in a fluid sample includes the steps of acquiring a brightfield background image of a membrane filter, introducing a fluid sample onto the membrane filter, acquiring a brightfield image of filtered particles resting on the membrane filter, generating a particle mask based on the brightfield background image and the brightfield image of filtered particles, introducing a fluorescent dye onto the membrane filter, detecting fluorescence on the particle mask, and distinguishing between proteinaceous and non-proteinaceous particulates based on the detected fluorescence. A method for detecting other types of particles, such as polysorbate particles, silicone oil or protein monomers is also disclosed.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 9, 2020
    Inventors: Colby Ashcroft, Brian DiPaolo, Gjergji Konica, Thomas Castner, Bernardo Cordovez, Christopher Earhart, David Erickson, Robert Hart
  • Patent number: 10701921
    Abstract: A fishing rig storage device that is removably insertable into a receiving slot incorporated in at least one of a dividing wall or an interior surface of a tackle container is illustrated and described. The fishing rig storage device includes a mounting tab having quartered sections and a plurality of notches formed along a perimeter. Each quartered section includes at least one of the plurality of notches. A fishing rig having a hook assembly, a line, and a tail is secured to the mounting tab by securing the hook assembly to a first notch, selectively wrapping the line around the plurality of notches, and securing the tail to a slit extending from the perimeter. The line is preferably arranged around the mounting tab to minimize catching or snagging of the line on the hook assembly when the line is unwrapped from the mounting tab.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: July 7, 2020
    Inventors: Josh Erickson, David Levy
  • Patent number: 10671348
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a first set of scaled capacitors connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to a second set of scaled capacitors configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor of first set of scaled capacitors has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Publication number: 20200167126
    Abstract: A negative-operand compatible subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes two sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of two sets of scaled capacitors electrically connected to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground. A control circuit of the subtractor is configured to, in conjunction with the reset circuit, draw the difference output node to a reset voltage.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Phil Paone, David Paulsen, George Paulik, John E. Sheets, II, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10653554
    Abstract: An injector apparatus comprises an elongate structure having one or more openings positionable near a penetrable barrier of an implantable device so as to receive fluid of the implantable device. The apparatus comprises a needle and a sheath extending over at least a portion of the needle. The elongate structure may comprise a distal tip to penetrate tissue and the penetrable barrier, and a distal opening near the tip to release therapeutic fluid into the implantable chamber. In many embodiments the distal tip, the distal opening, and the plurality of openings are separated from a stop that engages a tissue of the patient and limit penetration depth such that the distal opening and the plurality of openings are located along an axis of the implantable device to increase an efficiency of the exchange.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: May 19, 2020
    Assignee: ForSight Vision4, Inc.
    Inventors: Darren Doud, Randolph E. Campbell, Signe Erickson, K. Angela Macfarlane, Mike Barrett, Christina Skieller, David Batten, Greg Stine, Eugene de Juan, Jr., Douglas Sutton, Kathleen Cogan Farinas
  • Patent number: 10658993
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Patent number: 10642519
    Abstract: A method and apparatus that provides a solid state drive that analyzes connection performance during I/O operations and is configured to independently modify connection performance based upon user specified input parameters without the need for host computer management.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: May 5, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Mark David Erickson
  • Patent number: 10635154
    Abstract: The present disclosure generally relates to a method for intelligent device initiated SAS Phy PM. Using device internal phy characteristics and future phy usage queue, the device determines optimal SAS Phy PM usage based on a predetermined configuration preference of power versus performance. The device achieves optimal SAS Phy PM Usage by implementing a state machine to manage phy PM states and transitions between the PM states. The device state machine includes capabilities to proactively initiate transitions to partial or slumber PM states, start early wake-up from partial or slumber PM states to mask the associated latency impacts of exiting partial or slumber PM states, and selectively reject host requests to enter a partial or slumber PM state.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: April 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mark David Erickson, Darin Edward Gerhart, Nicholas Edward Ortmeier, Yasunobu Suginaka
  • Publication number: 20200125328
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a first set of scaled capacitors connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to a second set of scaled capacitors configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor of first set of scaled capacitors has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Publication number: 20200127626
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Patent number: 10603209
    Abstract: Described herein is an apparatus to insert an implantable therapeutic device into a patient. The apparatus includes a proximal handle and a distal placement portion coupled to the proximal handle and configured to hold the implantable therapeutic device. The distal placement portion includes a first side having a first engagement structure at a distal end of the first side, the first engagement structure configured to surround at least a first portion of a proximal end region of the implantable therapeutic device. The distal placement portion includes a second, opposite side having a second engagement structure at a distal end of the second side, the second engagement structure configured to surround at least a second, opposite portion of the proximal end region of the implantable therapeutic device.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 31, 2020
    Assignee: Forsight Vision4, Inc.
    Inventors: Eugene de Juan, Jr., Randolph E. Campbell, Signe Erickson, Michael S. Barrett, Christina Skieller, David Batten, Darren Doud
  • Patent number: 10604733
    Abstract: An optofluidic photoreactor including an optical waveguide having an input, characterized by an evanescent optical field confined along an outer surface of the optical waveguide produced by radiation propagating in the optical waveguide, means for inputting light to the input of the optical waveguide, and a photoactive material disposed substantially only within the evanescent field. A method for optically activating a photoactive material in an optofluidic photoreactor to convert carbon dioxide and water into other molecules that may be useful as a fuel or a chemical feedstock.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: March 31, 2020
    Assignee: CORNELL UNIVERSITY
    Inventors: David Erickson, Perry M. Schein
  • Patent number: 10592209
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of two received binary numbers. The multiplier circuit includes two sets of inputs that receive binary numbers. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of an AND gate and to a local product output node. Each AND gate is connected to a unique pair of bits, one bit from each of the two binary numbers. Each scaled capacitor has a capacitance proportional to a product term generated by the corresponding AND gate. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Patent number: 10587282
    Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10566987
    Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Publication number: 20200042192
    Abstract: A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Inventors: Darin Edward GERHART, Nicholas Edward ORTMEIER, Mark David ERICKSON