Patents by Inventor David F. Brown

David F. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190359899
    Abstract: Systems and methods are provided for hydroconversion of a heavy oil feed under slurry hydroprocessing conditions and/or solvent assisted hydroprocessing conditions. The systems and methods for slurry hydroconversion can include the use of a configuration that can allow for improved separation of catalyst particles from the slurry hydroprocessing effluent. In addition to allowing for improved catalyst recycle, an amount of fines in the slurry hydroconversion effluent can be reduced or minimized. This can facilitate further processing or handling of any “pitch” generated during the slurry hydroconversion. The systems and methods for solvent assisted hydroprocessing can include processing of a heavy oil feed in conjunction with a high solvency dispersive power crude.
    Type: Application
    Filed: August 6, 2019
    Publication date: November 28, 2019
    Inventors: Benjamin S. UMANSKY, Himanshu GUPTA, John D. NELSON, Cindy J. HUGHART, Jane C. CHENG, Steven W. LEVINE, Stephen H. BROWN, Todd P. MARUT, David C. DANKWORTH, Stuart L. SOLED, Thomas F. DEGNAN, JR., Robert J. FALKINER, Mohsen N. HARANDI, Juan D. HENAO, Lei ZHANG, Chuansheng BAI, Richard C. DOUGHERTY
  • Publication number: 20190338203
    Abstract: Systems and methods are provided for hydroconversion of a heavy oil feed under slurry hydroprocessing conditions and/or solvent assisted hydroprocessing conditions. The systems and methods for slurry hydroconversion can include the use of a configuration that can allow for improved separation of catalyst particles from the slurry hydroprocessing effluent. In addition to allowing for improved catalyst recycle, an amount of fines in the slurry hydroconversion effluent can be reduced or minimized. This can facilitate further processing or handling of any “pitch” generated during the slurry hydroconversion. The systems and methods for solvent assisted hydroprocessing can include processing of a heavy oil feed in conjunction with a high solvency dispersive power crude.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: Benjamin S. UMANSKY, Himanshu GUPTA, John D. NELSON, Cindy J. HUGHART, Jane C. CHENG, Steven W. LEVINE, Stephen H. BROWN, Todd P. MARUT, David C. DANKWORTH, Stuart L. SOLED, Thomas F. DEGNAN, JR., Robert J. FALKINER, Mohsen N. HARANDI, Juan D. HENAO, Lei ZHANG, Chuansheng BAI, Richard C. DOUGHERTY
  • Publication number: 20190327575
    Abstract: A system and method of modifying a binaural signal using headtracking information. The system calculates a delay, a first filter response, and a second filter response, and applies these to the left and right components of the binaural signal according to the headtracking information. The system may also apply headtracking to parametric binaural signals. In this manner, headtracking may be applied to pre-rendered binaural audio.
    Type: Application
    Filed: June 20, 2017
    Publication date: October 24, 2019
    Applicant: DOLBY LABORATORIES LICENSING CORPORATION
    Inventors: C. Phillip Brown, Joshua Brandon Lando, Mark F. Davis, Alan J. Seefeldt, David Matthew Cooper, Dirk Jeroen Breebaart, Rhonda Wilson
  • Patent number: 10420507
    Abstract: A personal impact monitoring system is described herein comprising a monitoring station that receives impact events sent from personal impact monitors, using a monitoring station receiver. The impact events, which specify impact parameters associated with the impact events, are stored in a data storage location associated with the monitoring station. Software operating on the operating station is configured to retrieve the impact events from the data storage location and to perform calculations based on the impact events to identify notable impact events.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 24, 2019
    Assignee: il Sensortech, Inc.
    Inventors: Lawrence V. Calcano, David Thomas Brown, Christopher C. Genau, David Ernest Snyder, James M. Stearns, Brian Michael Ronald, Jesse David Harper, John F. Harris
  • Patent number: 10414991
    Abstract: Systems and methods are provided for hydroconversion of a heavy oil feed under slurry hydroprocessing conditions and/or solvent assisted hydroprocessing conditions. The systems and methods for slurry hydroconversion can include the use of a configuration that can allow for improved separation of catalyst particles from the slurry hydroprocessing effluent. In addition to allowing for improved catalyst recycle, an amount of fines in the slurry hydroconversion effluent can be reduced or minimized. This can facilitate further processing or handling of any “pitch” generated during the slurry hydroconversion. The systems and methods for solvent assisted hydroprocessing can include processing of a heavy oil feed in conjunction with a high solvency dispersive power crude.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 17, 2019
    Assignee: ExxonMobil Research and Engineering Company
    Inventors: Benjamin S. Umansky, Himanshu Gupta, John D. Nelson, Cindy J. Hughart, Jane C. Cheng, Steven W. Levine, Stephen H. Brown, Todd P. Marut, David C. Dankworth, Stuart L. Soled, Thomas F. Degnan, Jr., Robert J. Falkiner, Mohsen N. Harandi, Juan D. Henao, Lei Zhang, Chuansheng Bai, Richard C. Dougherty
  • Patent number: 10418473
    Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: September 17, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Andrea Corrion
  • Patent number: 10359972
    Abstract: A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 23, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Vikram Joshi, David Flynn, Yang Luan, Michael F. Brown
  • Patent number: 10346095
    Abstract: A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 9, 2019
    Assignee: SANDISK TECHNOLOGIES, LLC
    Inventors: Vikram Joshi, David Flynn, Yang Luan, Michael F. Brown
  • Patent number: 10314647
    Abstract: An electrosurgical device having a tubular outer shaft and an inner shaft is disclosed. The tubular outer shaft includes an axis and a distal end region. The distal end region includes a distal-most tip and a cutting edge defining a window in the outer shaft proximal along the axis to the distal-most tip. The inner shaft inner shaft coaxially maintained within the outer shaft such that the inner shaft is movable about the axis with respect to the outer shaft and wherein a portion of the inner shaft is exposed in the window of the outer shaft. A first electrode is disposed on the outer shaft in a region proximal along the axis to the window, and a second electrode is electrically isolated from the first electrode and disposed on the inner shaft. The second electrode is exposed in the window of the outer shaft.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: June 11, 2019
    Assignee: Medtronic Advanced Energy LLC
    Inventors: Eliot F. Bloom, Phillip Berman, Wenjeng Li, David J. Little, Dana A. Oliver, John R. Prisco, Phillip P. Brown, Patrick Richart
  • Patent number: 10217648
    Abstract: Methods using chemical vapor deposition (CVD) of diamond deposited on a sacrificial material provide CVD diamond microchannel structures and 3-D interconnection structures of CVD diamond microfluidic channels. The sacrificial material is patterned to define locations and dimensions of the microchannels. The patterned sacrificial material is selectively removed from underneath the chemical vapor deposited (CVD) diamond to form the CVD diamond microchannels. The CVD diamond microchannels are integrated with electronic structures to provide an integral microfluidic cooling system to electronic devices.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 26, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Alexandros Margomenos, Andrea Corrion, Hector L. Bracamontes, Ivan Alvarado-Rodriguez
  • Patent number: 9954090
    Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: April 24, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Andrea Corrion
  • Patent number: 9929243
    Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: March 27, 2018
    Assignee: HRL Laboratories, LLC
    Inventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Alexandros D. Margomenos, Shawn D. Burnham
  • Patent number: 9525033
    Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: December 20, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Miroslav Micovic
  • Patent number: 9473293
    Abstract: A phase lock loop monitor circuit is disclosed. The phase lock loop monitor circuit may include a coarse tuning circuit operable to generate a coarse tune failure indicator, a frequency target lock detector circuit operable to generate a frequency target failure indicator, a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator, and an abort logic circuit communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the abort logic circuit operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: October 18, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chris N. Stoll, Prachee S. Behera, David F. Brown, Shobak R. Kythakyapuzha, Khurram Waheed
  • Patent number: 9419122
    Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: August 16, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Adam J. Williams, Dean C. Regan, Joel C. Wong
  • Publication number: 20160191231
    Abstract: A phase lock loop monitor circuit is disclosed. The phase lock loop monitor circuit may include a coarse tuning circuit operable to generate a coarse tune failure indicator, a frequency target lock detector circuit operable to generate a frequency target failure indicator, a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator, and an abort logic circuit communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the abort logic circuit operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: CHRIS N. STOLL, PRACHEE S. BEHERA, DAVID F. BROWN, SHOBAK R. KYTHAKYAPUZHA, KHURRAM WAHEED
  • Patent number: 9378949
    Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: June 28, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Andrea Corrion
  • Patent number: 9276529
    Abstract: An operational amplifier includes three transconductance stages (TSs) each having a differential input and a differential output, a first and second resistor coupled between the differential output of the first TS and the differential input of the first TS, a third and fourth resistor coupled between the differential output of the third TS and the differential input of the first TS, a first and second capacitor coupled between the differential output of the third TS and the differential input of the third TS, wherein the first, second, and third TSs each include a differential input amplifier coupled to the differential input of the respective TS, a differential output amplifier coupled to the differential output of the respective TS, and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for voltage level shifting.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: March 1, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Miroslav Micovic, Ara K. Kurdoghlian, Alexandros Margomenos
  • Patent number: 9202880
    Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 1, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Adam J. Williams, Dean C. Regan, Joel C. Wong
  • Patent number: 9148092
    Abstract: A method of fabricating amplifiers, includes monolithically integrating a field-plate transistor and T-gate transistor on a single wafer. A device includes a monolithically integrated field-plate transistor and T-gate transistor on a single wafer.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: September 29, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Miroslav Micovic