Abstract: The present invention is directed to an electrodepositable coating composition comprising an electrodepositable binder comprising an ionic salt group-containing film-forming polymer comprising active hydrogen functional groups, and a blocked polyisocyanate curing agent; a solubilized bismuth catalyst; and a guanidine; wherein the electrodepositable coating composition has a weight ratio of bismuth metal from the solubilized bismuth catalyst to guanidine of from 1.00:0.071 to 1.0:2.1 and/or a molar ratio of bismuth metal to guanidine of from 1.0:0.25 to 1.0:3.0. Also disclosed are methods of treating electrodepositable coating compositions, methods for making electrodepositable coating compositions, systems for coating a metal substrate, coatings, coated substrates, and methods of coating a substrate.

Abstract: A wireless electromechanical lock with one or more of an internal antenna, touch activation, and/or a light communication device that acts as a user interface. In some embodiments, the lock utilizes an antenna near the exterior face of the lockset, designed inside the metal body of the lockset itself. A light communication device is provided in some embodiments to communicate information, visually, to the user via animations and dynamic displays of light. In some embodiments, the lockset includes a touch activation capability, which can be used to lock/unlock the lock and/or otherwise provide input.

Abstract: A self-aligned GaN FinFET device and a method of fabricating the same are disclosed. This self-aligned process helps to fabricate GaN FinFET devices in a scalable manner. This work transforms the T-gate process to incorporate fins to further improve pinch-off and decrease leakage currents on highly scaled GaN HEMT structures. The GaN FinFET structure will also allow for integration of normally-off devices with normally-on devices by varying the fin width. The FinFET improvement combines the fin structure consisting of various fin pitches and widths, gate dielectric, self-aligned gate design, ultra-low ohmic contacts, and vertically scaled epitaxy into a single scalable process.

Abstract: A four-terminal GaN transistor and methods of manufacture, the transistor having source and drain regions and preferably two T-shaped gate electrodes, wherein a stem of one of the two T-shaped gate electrodes is more closely located to the source region than it is to a stem of the other one of the two T-shaped gate electrodes and wherein the stem of the other one of the two T-shaped gate electrodes is more closely located to the drain region than it is to the stem of said one of the two T-shaped gate electrodes. The the gate closer to the source region is a T-gate, and the proximity of the two gates is less than 500 nm from each other. The spacing between the stem of the RF gate and source region and the stem of the DC gate and drain region are preferably defined by self-aligned fabrication techniques. The four-terminal GaN transistor is capable of operation in the W-band (75 to 100 GHz).

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Abstract: Methods using chemical vapor deposition (CVD) of diamond deposited on a sacrificial material provide CVD diamond microchannel structures and 3-D interconnection structures of CVD diamond microfluidic channels. The sacrificial material is patterned to define locations and dimensions of the microchannels. The patterned sacrificial material is selectively removed from underneath the chemical vapor deposited (CVD) diamond to form the CVD diamond microchannels. The CVD diamond microchannels are integrated with electronic structures to provide an integral microfluidic cooling system to electronic devices.

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.

Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.

Abstract: A phase lock loop monitor circuit is disclosed. The phase lock loop monitor circuit may include a coarse tuning circuit operable to generate a coarse tune failure indicator, a frequency target lock detector circuit operable to generate a frequency target failure indicator, a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator, and an abort logic circuit communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the abort logic circuit operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.

Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.

Abstract: A phase lock loop monitor circuit is disclosed. The phase lock loop monitor circuit may include a coarse tuning circuit operable to generate a coarse tune failure indicator, a frequency target lock detector circuit operable to generate a frequency target failure indicator, a cycle slip monitor circuit operable to generate a cycle slip lock failure indicator, and an abort logic circuit communicatively coupled to the coarse tuning circuit, the frequency target lock detector circuit, and the cycle slip monitor circuit, the abort logic circuit operable to generate a radio operation abort indicator based at least on the coarse tune failure indicator, the frequency target failure indicator, or the cycle slip lock failure indicator.

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Abstract: An operational amplifier includes three transconductance stages (TSs) each having a differential input and a differential output, a first and second resistor coupled between the differential output of the first TS and the differential input of the first TS, a third and fourth resistor coupled between the differential output of the third TS and the differential input of the first TS, a first and second capacitor coupled between the differential output of the third TS and the differential input of the third TS, wherein the first, second, and third TSs each include a differential input amplifier coupled to the differential input of the respective TS, a differential output amplifier coupled to the differential output of the respective TS, and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for voltage level shifting.

Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.

Abstract: A method of fabricating amplifiers, includes monolithically integrating a field-plate transistor and T-gate transistor on a single wafer. A device includes a monolithically integrated field-plate transistor and T-gate transistor on a single wafer.

Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.

Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.

Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.

Abstract: A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.