Abstract: A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.

Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.

Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.

Abstract: A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region.

Abstract: A circuit (12) for symbol decision directed feedback synchronization includes a current synchonization clock (45) that provides an initial sampling point and selects a detector corresponding to a current symbol decision. The circuit further includes a plurality of detectors (31, 32, 33, and 34) including the detector corresponding to the current symbol decision, a buffer (736) for storing the output of the detector corresponding to the current symbol decision and a processor (300) for seeking within a predetermined window about the initial sampling point for an optimum phase value to provide an adjustment signal which is used by the processor to adjust a subsequent symbol's sychronization clock to provide an optimal sampling point.

Abstract: A circuit assembly includes a mounting structure 10 having walls 11-13, 20 with conductor strips 19 running along the length of the structure. Plate members 14 carrying components such as integrated circuits 16 have conductive areas 18 which contact the conductor strips 19 when the members are inserted into the structure 10. The walls may include slots 15 into which the plate members 14 are slidably engaged. The support structure 10 thus provides physical support for the members 14 as well as electrical interconnection therebetween. Cooling arrangements for the assembly can include apertures 21 in the walls, and/or finning 22.

Abstract: A circuit unit such as performing the function of a chip carrier. In one example, it is in the form of a thin square of insulating material having contact pads arranged side by side along the four edges of both major surfaces. The chip is secured substantially centrally of the insulating material and connections are made from it to the contacts on both of the major surfaces. The carrier has a lower insulating layer (5) having contacts (6) extending over its under surface and carrying the chip (14) on its upper surface. An insulating spacer (8) carries further contacts (12). Electrical connections (16 and 18) are made to the contacts (6 and 12). An insulating cover (not shown) then closes off the hollow interior, locating on a shoulder (10). The contacts (12) thus provide the contacts on the upper surface of the finished construction. A single layer construction is also disclosed.

Abstract: The continuity of a ground strap (16) is tested by pushing down on a switch activating toggle lever (37). The toggle lever is conductive, is isolated from ground and is coupled to a signal input terminal of a test circuit module (14). Thus, when the hand of the operator touches the toggle lever to activate the test circuit module (14), the resistive path through the operator and the ground strap (16) is coupled into the test circuit as the input-terminal-to-ground resistor of a voltage divider circuit. A resulting voltage at the toggle lever causes an indication by lighting either indicator (33) or indicator (34) whether the operator is properly coupled to ground.

Abstract: A circuit assembly includes a mounting structure 10 having walls 11-13, 20 with conductor strips 19 running along the length of the structure. Plate members 14 carrying components such as integrated circuits 16 have conductive areas 18 which contact the conductor strips 19 when the members are inserted into the structure 10. The walls may include slots 15 into which the plate members 14 are slidably engaged. The support structure 10 thus provides physical support for the members 14 as well as electrical interconnection therebetween.Cooling arrangements for the assembly can include apertures 21 in the walls, and/or finning 22.

Abstract: A back-up electrical power supply module provides a back-up supply for a plug-in volatile electrical device such as a memory module. The memory module has a dual-in-line pins which engage socket openings of a standard dual-in-line circuit board connector. The back-up supply module is mounted on top of the memory module and has dual-in-line pins which contact corresponding ones of the pins of the memory module and corresponding socket openings. In this way the back-up supply module and the memory module can be unplugged as a unit and when unplugged, the back-up supply will maintain the contents of the volatile memory module intact.

Abstract: A high performance golf tee comprises a stem, a cup-shaped ball receptacle on the top of the stem, and a projection extending outwardly from the ball receptacle a sufficient distance such that when a golf ball is placed on the tee and a golf club is swung at the ball, the golf club contacts the projection and imparts motion to the ball before the golf club makes direct contact with the surface of the golf ball. The contact between the golf club and the projection imparts an initial backspin on the ball, and this improves the flight characteristics of the ball. The golf tee may be integrally molded as a unit including the projection or the projection may be formed as an attachment for a conventional golf tee.