Abstract: The present invention provides an apparatus, system and method for providing a generalized queue pair for use with host channel adapters of a system area network. With the apparatus, system and method, the hypervisor of a host channel adapter maintains a P_Key table for each logical port of the host channel adapter. When a request is received to allocate a queue pair from a requestor application associated with a logical port, a P_Key mode is set in a control register associated with the queue pair based on the type of requestor application that sent the request. Based on this P_Key mode, one or more P_Keys from a P_Key table associated with the logical port from which the request was received are written to one or more P_Key registers allocated to the queue pair. These P_Keys are then used to perform P_Key checks of incoming data packets. In addition, these P_Keys are inserted into headers of outgoing data packets.

Abstract: A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A preferred embodiment of the present invention allows LPAR “hypervisor” firmware to assume the responsibility for multicast protocol handling and distribution of packets among logical partitions.

Abstract: A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A preferred embodiment of the present invention allows LPAR “hypervisor” firmware to assume the responsibility for multicast protocol handling and distribution of packets among logical partitions.

Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.

Abstract: A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, respectively, thereon. The system utilizes time stamp values generated by the third and fourth clocks to synchronize the first and second time-of-day clocks.

Abstract: Disclosed are a method and system for address translation with memory windows. The method comprises the steps of designating a memory region having a set of virtual addresses, each virtual address having an associated real address; and providing one or more translation tables for translating the virtual addresses to the real addresses; A memory region protection table entry (MRPTE) defines access rights for the memory region, and includes one or more pointers to the one or more translation tables. A memory window is bound to the memory region to provide access to a subset of the virtual addresses. A memory window protection table entry (MWPTE) defines access rights for the memory window, and includes one or more pointers to the one or more translation tables to translate the subset of virtual addresses to real addresses.

Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.

Abstract: A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, respectively, thereon. The system utilizes time stamp values generated by the third and fourth clocks to synchronize the first and second time-of-day clocks.

Abstract: An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter (HCA). The apparatus, system and method ensures that each operating system is unaware that the HCA hardware resources are being shared with other operating systems and further guarantees that the individual operating systems are prevented from accessing HCA hardware resources which are associated with other operating systems.

Abstract: A method of managing memory mapped input output operations to an alternate address space comprising: executing a first instruction directed to a first memory mapped input output alternate address space of a machine associated with a first adapter to allocate a resource associated with the first adapter to a process in accordance with a definition of a z/Architecture; wherein a selected process issues at least one of a load and a store instruction executed in a problem state of the machine to a selected address location of a selected resource. The method further includes ensuring that the selected resource corresponds with the allocated resource and determining that the selected process corresponds with the process to which the resource is allocated.

Abstract: Apparatus and method for virtualizing a queue pair space to minimize time-wait impacts. Virtual queue pairs are allocated from a virtual queue pair pool of a node to connections between the node and other nodes. The connection is established between a physical queue pair of the node and physical queue pairs of other nodes. From the viewpoint of the other nodes, they are communicating with the present node using the virtual queue pair and not the physical queue pair for the present node. By using the virtual queue pairs, the same physical queue pair may accommodate multiple connections with other nodes simultaneously. Moreover, when a connection is torn down, the virtual queue pair is placed in a time-wait state rather than the physical queue pair. As a result, the physical queue pair may continue to function while the virtual queue pair is in the time-wait state.

Abstract: A mechanism for allowing a single physical IB node to virtualize a plurality of host channel adapters is provided. This includes providing the appearance of both a router and multiple virtual HCA's residing behind that router, to the external REAL subnet components. Each virtual host channel adapter will have unique access control levels. One or more InfiniBand subnets are virtualized in such a way that nodes residing both within the virtual subnets and in separate physical subnets are completely unaware of the virtualization. This virtualization of InfiniBand subnets significantly increases the horizontal scaling capabilities of a single InfiniBand physical component, while at the same time provides “native” network throughput for all the virtual hosts.

Abstract: An apparatus and method for managing reliable datagram work queues, and associated completion queues, using head and tail pointers with end-to-end context error cache are provided. Reliable datagram (RD) queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a RD queue page table index and a RD queue page index for identifying a position within the RD queue. For RD work queues, in the channel interface, the tail pointer is used to identify a next position where a work queue entry may be written and the head pointer is used only to determine whether the work queue is full. In the host channel adapter, the head pointer is used to identify a next work queue entry for processing and the tail pointer is used to determine if the queue is empty.

Abstract: An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With the present invention, a first level of access is provided through virtual address translation and a mechanism for determining if the requestor of access may access a system memory address space page associated with a real address to which the virtual address maps. A second level of access is provided through the allocation of usage classes and determining a required usage class for accessing an HCA facility.

Abstract: An apparatus and method for swapping out real memory by inhibiting input/output (I/O) operations to a memory region are provided. The apparatus and method provide a mechanism in which a quiesce indicator is provided in a field containing the current outstanding I/O count associated with the memory region whose real memory is to be swapped out. The current I/O field and the quiesce indicator are used as a means for communicating between a shared resource arbitrator and a guest consumer. When the quiesce indicator is set, the guest consumer is informed that it should not send any further I/O operations to that memory region. When the number of pending I/O operations against the memory region is zero, a valid bit in a protection table is set to invalid, and the real memory associated with the memory region may be swapped out.

Abstract: The present invention provides an apparatus, system and method for providing a generalized queue pair for use with host channel adapters of a system area network. With the apparatus, system and method, the hypervisor of a host channel adapter maintains a P_Key table for each logical port of the host channel adapter. When a request is received to allocate a queue pair from a requestor application associated with a logical port, a P_Key mode is set in a control register associated with the queue pair based on the type of requestor application that sent the request. Based on this P_Key mode, one or more P_Keys from a P_Key table associated with the logical port from which the request was received are written to one or more P_Key registers allocated to the queue pair. These P_Keys are then used to perform P_Key checks of incoming data packets. In addition, these P_Keys are inserted into headers of outgoing data packets.

Abstract: An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter (HCA). The apparatus, system and method ensures that each operating system is unaware that the HCA hardware resources are being shared with other operating systems and further guarantees that the individual operating systems are prevented from accessing HCA hardware resources which are associated with other operating systems.

Abstract: An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With the present invention, a first level of access is provided through virtual address translation and a mechanism for determining if the requestor of access may access a system memory address space page associated with a real address to which the virtual address maps. A second level of access is provided through the allocation of usage classes and determining a required usage class for accessing an HCA facility.

Abstract: A distributed computing system having (host and I/O) end nodes, switches, routers, and links interconnecting these components is provided. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a message has been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism implements these queue pairs and completion queues in hardware. A mechanism for controlling the transfer of work requests from the consumer to the CA hardware and work completions from the CA hardware to the consumer using head and tail pointers that reference circular buffers is also provided. The QPs and CQs do not contain Work Queue Entries and Completion Queue Entries respectively, but instead contain references to these entries.

Abstract: The present invention provides a method for managing transmissions to a remote node having a buffer memory for receiving the transmitted packets and means for acknowledging the receipt of the packets. The method provides for a sender to maintain a sense of the availability of buffer memory even when acknowledging messages are lost with minimal impact on performance.