Abstract: A method, computer program product, and data processing system for sharing memory protection tables and address translation tables among multiple Host Channel Adapters are disclosed. The protection and address translation tables for a shared memory region are written in memory of the host. The Host Channel Adapters are registered with the memory region so that each adapter stores an address pointer to the tables. In this way, the tables need not be duplicated for each adapter.

Abstract: An apparatus and method for managing work and completion queues using head and tail circular pointers. With the apparatus and method, queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a queue pointer table index and a queue page index for identifying a position within the queue. For work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty. For completion queues, the head pointer in the channel interface is used to identify a next completion queue entry to be processed.

Abstract: A method, program and system for associating memory windows with memory regions in an infiniband data storage system are provided. The invention comprises registering a Memory Region, wherein the Memory Region is a set of virtually contiguous memory addresses defined by a virtual address and length. The system then establishes and maintains a Window Reference Count (WRC) for the Memory Region, which tracks the number of Memory Windows which are bound to the Memory Region. When the system binds a Memory Window to the Memory Region, the value of the WRC is incremented. When a Memory Window is unbound from the Memory Region, the value of the WRC is decremented. If no Memory Windows are bound to the Memory Region, the value of the WRC is zero. The Memory Region is not deregistered unless the value of the WRC equals zero.

Abstract: A method, system and program for controlling access to memory areas within a computer are provided. The invention comprises placing a first Bind Work Queue Element (WQE) at the head of a work queue, wherein the first Bind WQE defines parameters associated with a first Memory Window. A set of Work Requests is then placed on the work queue, behind the first Bind WQE wherein the work requests invoke operations that access the first Memory Window. A second Bind WQE is then placed on the work queue, behind the first set of Work Requests. This second Bind WQE defines parameters associated with a second Memory Window. A second set of Work Requests is placed on the work queue behind the second Bind WQE and invoke operations that access the second memory window. The Memory Windows can be associated with a common Memory Region and have different addresses and lengths or different access rights. In another embodiment, the first and second Memory Windows can be associated with different Memory Regions.

Abstract: A method, system and program for controlling access to computer memory are provided. The present invention comprises receiving a work request from a user, wherein the work request comprises an index portion and a protection portion. The index portion of the work request is used to locate an element in an address translation and protection table. The protection portion of the work request is then compared with a protection key in the table element, and access to memory is granted only if the protection portion and protection key match.

Abstract: An apparatus and method for managing reliable datagram work queues, and associated completion queues, using head and tail pointers with end-to-end context error cache are provided. With the apparatus and method, reliable datagram (RD) queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a RD queue page table index and a RD queue page index for identifying a position within the RD queue. For RD work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty.

Abstract: A method, computer program product, and data processing system for sharing memory protection tables and address translation tables among multiple Host Channel Adapters are disclosed. The protection and address translation tables for a shared memory region are written in memory of the host. The Host Channel Adapters are registered with the memory region so that each adapter stores an address pointer to the tables. In this way, the tables need not be duplicated for each adapter.

Abstract: A distributed computing system having (host and I/O) end nodes, switches, routers, and links interconnecting these components is provided. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a message has been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism implements these queue pairs and completion queues in hardware. A mechanism for controlling the transfer of work requests from the consumer to the CA hardware and work completions from the CA hardware to the consumer using head and tail pointers that reference circular buffers is also provided. The QPs and CQs do not contain Work Queue Entries and Completion Queue Entries respectively, but instead contain references to these entries.

Abstract: A mechanism for initiating and completing one or more I/O transactions using memory semantic messages is disclosed. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than the simple transmission of a message.

Abstract: A mechanism for allowing a single physical IB node to virtualize a plurality of host channel adapters is provided. This includes providing the appearance of both a router and multiple virtual HCA's residing behind that router, to the external REAL subnet components. Each virtual host channel adapter will have unique access control levels. One or more InfiniBand subnets are virtualized in such a way that nodes residing both within the virtual subnets and in separate physical subnets are completely unaware of the virtualization. This virtualization of InfiniBand subnets significantly increases the horizontal scaling capabilities of a single InfiniBand physical component, while at the same time provides “native” network throughput for all the virtual hosts.

Abstract: A distributed computing system is provided having (host and I/O) end nodes, switches, routers, and links interconnecting these components. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a message has been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism may implement these queue pairs and completion queues in hardware. A mechanism controls the transfer of work requests from the consumer to the channel adapter hardware using only head pointers in the hardware is described, along with a mechanism for passing work completions from the channel adapter hardware to the consumer using only tail pointers in the hardware. With this scheme the channel adapter hardware can inform the CI that a work request has been completed and provide the work completion information with just a single write to system memory.

Abstract: A mechanism for initiating and completing one or more I/O transactions using memory semantic messages in a system area network is disclosed. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than a simple “channel semantic” transmission of a message. The use of memory semantic input/output in this way facilitates the migration of input/output adapters from a memory-mapped interface, such as Peripheral Component Interconnect (PCI), to a system area network.

Abstract: A mechanism for initiating and completing one or more I/O transactions using channel and memory semantic messages is disclosed. Channel semantic messages are messages that are simply packetized and transmitted. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than the simple transmission of a message.

Abstract: An apparatus and method for virtualizing a queue pair space to minimize time-wait impacts. The apparatus and method allocate virtual queue pairs from a virtual queue pair pool of a node to connections between the node and other nodes. The connection is established between a physical queue pair of the node and physical queue pairs of other nodes. However, from the viewpoint of the other nodes, they are communicating with the present node using the virtual queue pair and not the physical queue pair for the present node. By using the virtual queue pairs, the same physical queue pair may accommodate multiple connections with other nodes simultaneously. Moreover, by using a virtual queue pair rather than a physical queue pair, when a connection is torn down, the virtual queue pair is placed in a time-wait state rather than the physical queue pair. As a result, the physical queue pair may continue to function while the virtual queue pair is in the time-wait state.

Abstract: An apparatus and method for managing work and completion queues using head and tail circular pointers. With the apparatus and method, queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a queue pointer table index and a queue page index for identifying a position within the queue. For work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty. For completion queues, the head pointer in the channel interface is used to identify a next completion queue entry to be processed.

Abstract: A method and system for transmitting and receiving data from a host computer system to an Ethernet adapter are provided. The method comprises establishing a connection between the host system and the Ethernet adapter pushing a transmit or receive request message from a host system device driver to the Ethernet adapter's request queue. Access to host memory is transferred to the Ethernet adapter. If data is being transmitted to the Ethernet adapter, the adapter reads the data from a location in host memory specified in the transmit request message, and then transmits the data onto transmission media (e.g. wire, fiber). If the request message is a receive request, the adapter reads the data from the media and then sends the data into host memory at the location specified in the receive request message. When the data transfer is complete, the adapter sends a response message back to the host.

Abstract: A method and system for a distributed computing system having components like end nodes, switches, routers and links interconnecting packets over the interconnecting links. The switches and routers interconnect the end nodes and route the packets to the appropriate end node. The end nodes reassemble the packets into a message at a destination. A mechanism is provided to allow a single physical component to appear as multiple components each with unique control levels. These components may be host channel adapters (HCAs), target channel adapters (TCAs) or switches. A method and system for end node partitioning for a physical element is provided. A configuration of the physical element is selected. A port associated with the physical element is probed, wherein the port is probed with a subnet management packet by a subnet manager. In response to detecting a switch associated with the port, a local identifier is assigned to the port resulting in a configuration change of the physical element.

Abstract: An apparatus and method for an advanced tunneling technique to allow Internet Protocol (IP) frames to be routed through System Area Network (SAN) components with little or no overhead are provided. Furthermore, an apparatus and method for processing Internet Protocol (IP) version 6 datagrams over a SAN using basic raw and unreliable datagram (RawD and UD respectively) interfaces are provided. The apparatus and method allows a host channel adapter (HCA) to attach directly to an IP router which supports multiple link protocols, for example a router than attaches InfiniBand (IB) links and Ethernet links, and uses IP as the networking protocol on both. In this way, a SAN may be coupled to a LAN via a router with minimal hardware and overhead.

Abstract: A method, program and system for associating memory windows with memory regions in an infiniband data storage system are provided. The invention comprises registering a Memory Region, wherein the Memory Region is a set of virtually contiguous memory addresses defined by a virtual address and length. The system then establishes and maintains a Window Reference Count (WRC) for the Memory Region, which tracks the number of Memory Windows which are bound to the Memory Region. When the system binds a Memory Window to the Memory Region, the value of the WRC is incremented. When a Memory Window is unbound from the Memory Region, the value of the WRC is decremented. If no Memory Windows are bound to the Memory Region, the value of the WRC is zero. The Memory Region is not deregistered unless the value of the WRC equals zero.

Abstract: A method, system and program for controlling access to computer memory are provided. The present invention comprises receiving a work request from a user, wherein the work request comprises an index portion and a protection portion. The index portion of the work request is used to locate an element in an address translation and protection table. The protection portion of the work request is then compared with a protection key in the table element, and access to memory is granted only if the protection portion and protection key match.