Patents by Inventor David French

David French has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118535
    Abstract: A substrate processing system for processing a substrate within a processing chamber is provided and includes a source terminal, a substrate support, and a tuning circuit. The substrate support holds the substrate and includes first and second electrodes, which receive power from a power source via the source terminal. The tuning circuit is connected to the first electrode or the second electrode. The tuning circuit is allocated for tuning signals provided to the first electrode. The tuning circuit includes at least one of a first impedance set or a second impedance set. The first impedance set is serially connected between the first electrode and the power source and receives a first signal from the power source via the source terminal. The second impedance set is connected between an output of the power source and a reference terminal and receives the first signal from the power source via the source terminal.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Inventors: David FRENCH, Vincent E. BURKHART, Karl Frederick LEESER, Liang MENG
  • Patent number: 12243725
    Abstract: A thermal choke rod connecting a radio frequency source to a substrate support of a plasma processing system includes a tubular member having a first connector for connecting to an RF rod coupled to the substrate support and a second connector for connecting to an RF strap that couples to the RF source. A tubular segment extends between the first and second connectors. The first connector has a conically-shaped end region that tapers away from the inner surface thereof to an outer surface in a direction toward the tubular segment, and slits that extend for a prescribed distance from a terminal end of the first connector. The outer surface of the tubular segment has a threaded region for threaded engagement with an annular cap that fits over the first connector and reduces an inner diameter of the first connector upon contact with the conically-shaped end region of the first connector.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: March 4, 2025
    Assignee: Lam Research Corporation
    Inventors: Timothy S. Thomas, Vincent Burkhart, Joel Hollingsworth, David French, Damien Slevin
  • Patent number: 12217939
    Abstract: A substrate processing system for processing a substrate within a processing chamber is provided and includes a source terminal, a substrate support, and a tuning circuit. The substrate support holds the substrate and includes first and second electrodes, which receive power from a power source via the source terminal. The tuning circuit is connected to the first electrode or the second electrode. The tuning circuit is allocated for tuning signals provided to the first electrode. The tuning circuit includes at least one of a first impedance set or a second impedance set. The first impedance set is serially connected between the first electrode and the power source and receives a first signal from the power source via the source terminal. The second impedance set is connected between an output of the power source and a reference terminal and receives the first signal from the power source via the source terminal.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: February 4, 2025
    Assignee: Lam Research Corporation
    Inventors: David French, Vincent E. Burkhart, Karl Frederick Leeser, Liang Meng
  • Publication number: 20250038034
    Abstract: Electrostatic chuck (ESC) apparatuses and systems are provided. An ESC may have one or more chucking electrodes and a blocking electrode that surrounds the chucking electrodes. The blocking electrode may reduce non-uniformities in semiconductor processing operations performed with the ESC. In some implementations, the blocking electrode is positioned beneath the chucking electrodes.
    Type: Application
    Filed: January 24, 2023
    Publication date: January 30, 2025
    Inventors: Stephen Topping, Patrick G. Breiling, Sergey Georgiyevich Belostotskiy, Ramesh Chandrasekharan, Timothy Scott Thomas, Mahmoud Vahidi, Yukinori Sakiyama, David French, Meenakshi Mamunuru, Ashish Saurabh, Pramod Subramonium, Noah Elliot Baker
  • Publication number: 20240407268
    Abstract: Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.
    Type: Application
    Filed: August 14, 2024
    Publication date: December 5, 2024
    Inventors: Fuchao Wang, Christopher Eric Brannon, William David French, Dok Won Lee
  • Publication number: 20240371604
    Abstract: An apparatus including a multi-station processing chamber with a top plate and a bottom portion encloses stations each including a pedestal assembly. A spindle centrally located between the stations is configured to rotate about a central axis, and is electrically connected to the bottom portion. An actuator controls movement of the spindle in the Z-direction. An indexer connected to the spindle rotates with the spindle, and includes extensions each configured to interface with a corresponding substrate for substrate transfer. An electrically conductive interface movably connected to the top plate provides an RF return path. Another actuator coupled to the grounding interface controls movement of the electrically conductive interface in the Z-direction. The electrically conductive interface moves downwards in the Z-direction to make contact with the indexer when each of the plurality of extensions is parked and the spindle is moved to a lower position during plasma processing.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 7, 2024
    Inventors: Sam Jafarian Tehrani, Karl Frederick Leeser, David French, John Michael Wiltse
  • Patent number: 12069956
    Abstract: Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: August 20, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Fuchao Wang, Christopher Eric Brannon, William David French, Dok Won Lee
  • Publication number: 20240272210
    Abstract: An apparatus to estimate parameters of a radio frequency (RF) signal may include a voltage sensor configured to provide an indication of a voltage of the RF signal as well as a current sensor configured to provide an indication of current conducted by the RF signal. The apparatus may additionally include an analog-to-digital conversion module coupled to an output port of the voltage sensor and the current sensor, wherein the analog-to-digital converter is configured to provide digital representations of an instantaneous voltage and an instantaneous current of the RF signal. The apparatus may additionally include one or more processors configured to transform the digital representations of the instantaneous voltage and current into frequency domain representations of a complex voltage and complex current.
    Type: Application
    Filed: April 23, 2024
    Publication date: August 15, 2024
    Inventors: Sunil Kapoor, David French
  • Publication number: 20240234091
    Abstract: Methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate include pulsing a low frequency radio frequency component at a high power. Pulsing low frequency power may be used to increase the selectivity or reduce the stress of an AHM. The AHM may then be used to etch features into underlying layers of the substrate.
    Type: Application
    Filed: October 24, 2023
    Publication date: July 11, 2024
    Inventors: Matthew Scott Weimer, Pramod Subramonium, Ragesh Puthenkovilakam, Rujun Bai, David French
  • Publication number: 20240203711
    Abstract: An apparatus to estimate parameters of a radio frequency (RF) signal may include a voltage sensor configured to provide an indication of a voltage of the RF signal as well as a current sensor configured to provide an indication of current conducted by the RF signal. The apparatus may additionally include an analog-to-digital converter coupled to an output port of the voltage sensor and the current sensor, wherein the analog-to-digital converter is configured to provide digital representations of an instantaneous voltage and an instantaneous current of the RF signal. The apparatus may additionally include one or more processors configured to transform the digital representations of the instantaneous voltage and current into frequency domain representations of a complex voltage and complex current.
    Type: Application
    Filed: March 24, 2021
    Publication date: June 20, 2024
    Inventors: Sunil Kapoor, David French, Gary Lemson, Liang Meng
  • Patent number: 11994542
    Abstract: An apparatus to estimate parameters of a radio frequency (RF) signal may include a voltage sensor configured to provide an indication of a voltage of the RF signal as well as a current sensor configured to provide an indication of current conducted by the RF signal. The apparatus may additionally include an analog-to-digital conversion module coupled to an output port of the voltage sensor and the current sensor, wherein the analog-to-digital converter is configured to provide digital representations of an instantaneous voltage and an instantaneous current of the RF signal. The apparatus may additionally include one or more processors configured to transform the digital representations of the instantaneous voltage and current into frequency domain representations of a complex voltage and complex current.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 28, 2024
    Assignee: Lam Research Corporation
    Inventors: Sunil Kapoor, David French
  • Publication number: 20240136153
    Abstract: Methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate include pulsing a low frequency radio frequency component at a high power. Pulsing low frequency power may be used to increase the selectivity or reduce the stress of an AHM. The AHM may then be used to etch features into underlying layers of the substrate.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Inventors: Matthew Scott Weimer, Pramod Subramonium, Ragesh Puthenkovilakam, Rujun Bai, David French
  • Patent number: 11955530
    Abstract: An integrated circuit includes a substrate having a first conductivity type. A well formed at an upper surface has a second, opposite conductivity type and a first dopant concentration. First and second STI structures are formed and a polysilicon gate structure is formed between the first and second STI structures. The polysilicon gate structure extends over a first side of the first STI structure and over a first side of the second STI structure. A first doped region is formed within the well at the upper surface and on a second side of the first STI structure and a second doped region is formed within the well at the upper surface and on a second side of the second STI structure. The first and second doped regions each have the second conductivity type and a second dopant concentration that is greater than the first dopant concentration.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: April 9, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Jeff Archimedes Babcock, Will David French, Dahlstrom Erik Mattias
  • Publication number: 20240055285
    Abstract: A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Inventors: Edward Augustyniak, David French, Sunil Kapoor, Yukinori Sakiyama, George Thomas
  • Patent number: 11877736
    Abstract: Provided is a spacer device for assisting a surgeon during knee surgery on a patient, the spacer device having a housing, a support portion and an electronic force sensor. The housing includes a lateral member having an outer surface and an inner surface and a pair of side members that comprise respective, internal, opposed side walls. The support portion includes a first end portion disposed between the side walls of the housing and including a first pair of lateral projections and a second end portion. The support portion is further adapted for axial slidable movement relative to the housing so as to define a first space and a second space between a first pair of lateral projections and respective side members for receiving one or more spacer elements therein. A surgical system including the spacer device as well as methods of using same are also provided.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: January 23, 2024
    Assignee: DSB Co Pty Ltd
    Inventors: Michael McAuliffe, Linda Cebisch-Nitz, David French
  • Patent number: 11837441
    Abstract: Methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate include pulsing a low frequency radio frequency component at a high power. Pulsing low frequency power may be used to increase the selectivity or reduce the stress of an AHM. The AHM may then be used to etch features into underlying layers of the substrate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 5, 2023
    Assignee: Lam Research Corporation
    Inventors: Matthew Scott Weimer, Pramod Subramonium, Ragesh Puthenkovilakam, Rujun Bai, David French
  • Patent number: 11823928
    Abstract: A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: November 21, 2023
    Assignee: Lam Research Corporation
    Inventors: Edward Augustyniak, David French, Sunil Kapoor, Yukinori Sakiyama, George Thomas
  • Publication number: 20230369091
    Abstract: A substrate support configured to support a substrate having a diameter D comprises a first inner electrode and a second inner electrode that are each D-shaped, define a first outer diameter that is less than D, and are configured to be connected to an electrostatic chuck voltage to clamp the substrate to the substrate support. An outer electrode comprises a ring-shaped outer portion that surrounds the first inner electrode and the second inner electrode and a center portion that pass between the first inner electrode and the second inner electrode to connect to opposite sides of an inner diameter of the ring-shaped outer portion. The inner diameter of the ring-shaped outer portion is greater than the diameter D such that the inner diameter of the ring-shaped outer portion and intersections between the center portion and the ring-shaped outer portion are located radially outside of the diameter D of the substrate.
    Type: Application
    Filed: September 28, 2021
    Publication date: November 16, 2023
    Inventors: Feng BI, Yukinori SAKIYAMA, Niraj RANA, Pengyi ZHANG, Simran SHAH, Timothy Scott THOMAS, David FRENCH, Vincent BURKHART
  • Patent number: 11788292
    Abstract: A dual strip protective edge film system for a roofing membrane having a first protective edge film strip covering a top edge portion of the roofing membrane and a second protective edge film strip covering a top portion of the roofing membrane, wherein the second protective edge film strip is positioned in parallel next to the first protective edge film strip, and wherein both of the edge strips have a combined width approximately equal to the width of the overlap between two overlapping roofing membranes that are adhesively secured or thermally welded together.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: October 17, 2023
    Assignee: CARLISLE CONSTRUCTION MATERIALS, LLC
    Inventors: Adam Burzynski, David French, Jordan Olivio, Jesse Sutton, Jacob Sandrock
  • Patent number: 11782102
    Abstract: A microelectronic device has a Hall sensor that includes a Hall plate in a semiconductor material. The Hall sensor includes contact regions in the semiconductor material, contacting the Hall plate. The Hall sensor includes an isolation structure with a dielectric material contacting the semiconductor material, on at least two opposite sides of each of the contact regions. The isolation structure is laterally separated from the contact regions by gaps. The Hall sensor further includes a conductive spacer over the gaps, the conductive spacer being separated from the semiconductor material by an insulating layer.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: October 10, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Keith Ryan Green, Erika Lynn Mazotti, William David French, Ricky Alan Jackson