Patents by Inventor David G. Ellis
David G. Ellis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040267479Abstract: A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventors: Bruce Querbach, David G. Ellis, Amjad Khan, Michael J. Tripp, Eric S. Gayles, Eshwar Gollapudi
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Patent number: 6826100Abstract: A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.Type: GrantFiled: March 31, 2003Date of Patent: November 30, 2004Assignee: Intel CorporationInventors: David G. Ellis, Bruce Querbach, Jay J. Nejedlo, Amjad Khan, Sean R. Babcock, Eric S. Gayles, Eshwar Gollapudi
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Publication number: 20040204912Abstract: According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.Type: ApplicationFiled: March 25, 2003Publication date: October 14, 2004Inventors: Jay J. Nejedlo, Mike Wiznerowicz, David G. Ellis, Richard J. Glass, Andrew W. Martwick, Theodore Z. Schoenborn
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Publication number: 20040117707Abstract: A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.Type: ApplicationFiled: March 31, 2003Publication date: June 17, 2004Inventors: David G. Ellis, Bruce Querbach, Jay J. Nejedlo, Amjad Khan, Sean R. Babcock, Eric S. Gayles, Eshwar Gollapudi
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Publication number: 20040117708Abstract: An integrated circuit (IC) component of a computer system, intended for use as part of a production version of the system, is provided with a built-in test unit and core function circuitry that are coupled to transfer information over the same I/O buffer circuitry of the component. The test unit is to transfer test information during a test session and to recognize announcement of the test session via an assertion and a deassertion, for predetermined time intervals, of an inter-component signal.Type: ApplicationFiled: March 31, 2003Publication date: June 17, 2004Inventors: David G. Ellis, Bruce Querbach, Jay J. Nejedlo, Amjad Khan, Sean R. Babcock, Eric S. Gayles, Eshwar Gollapudi
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Publication number: 20040040023Abstract: A system and method to remotely install software from a third device to a first device using identification information on a second device. The system and method do not require a user input to the first device.Type: ApplicationFiled: August 22, 2002Publication date: February 26, 2004Inventors: David G. Ellis, Steve A. Schoenberg
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Publication number: 20040008722Abstract: A redundant network interface for ethernet devices is disclosed. The redundant network interface provides connections between one or more Ethernet devices and two or more independent networks. The redundant network interface device also tests an active primary Ethernet connection path, and when a failure or inactive path is detected, the redundant network interface device reroutes the messages to alternate communication path.Type: ApplicationFiled: July 15, 2002Publication date: January 15, 2004Inventors: David G. Ellis, Steve A. Schoenberg
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Publication number: 20040010627Abstract: An Ethernet interface device, and associated system and method, for reporting the status information data of Ethernet devices through common industrial protocols. The Ethernet interface device provides operational connections between one or more Ethernet devices and one or more independent networks. The Ethernet interface device also monitors an Ethernet connection path, and produces status data indicative of the operational status of the connection path and the devices connected along the path. This status data is received by the Ethernet interface device, where it is manipulated into a format recognizable by common industrial protocols.Type: ApplicationFiled: July 15, 2002Publication date: January 15, 2004Inventors: David G. Ellis, Steve A. Schoenberg
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Patent number: 6523006Abstract: Video data is received from multiple video receptors. This multidimensional video data is converted from the video receptors into a multidimensional audio representation of the multidimensional video data and are the multidimensional audio representation is output using multiple audio output devices. The conversion of the multidimensional video data includes generating a three-dimensional representation of the multidimensional video data, and generating an audio landscape representation with three-dimensional features based on the three-dimensional representation.Type: GrantFiled: January 27, 1998Date of Patent: February 18, 2003Assignee: Intel CorporationInventors: David G. Ellis, Louis J. Johnson, Balaji Parthasarathy, Peter B. Bloch, Steven R. Fordyce, Bill Munson
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Publication number: 20010050710Abstract: An audio sensitive video conferencing camera is disclosed. The video conferencing camera includes a servo mechanism that operates to directionally position the video conferencing camera, and a processor that operates to control the servo mechanism to directionally position the video conferencing camera responsive to audio sensed.Type: ApplicationFiled: January 7, 1998Publication date: December 13, 2001Applicant: MARK J. FINKInventors: DAVID G. ELLIS, LOUIS J. JOHNSON, BALAJI R. PARTHASARATHY, PETER B. BLOCH, STEVEN R. FORDYCE, BILL A. MUNSON
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Patent number: 6256687Abstract: The present invention is directed to a method and apparatus for managing data flow between a serial bus device which operates at a first data rate and a parallel port device which operates at a second data rate. A serial bus receiver receives data from the serial bus device at the first data rate. A buffer unit is coupled to the serial bus receiver and the parallel port device. The buffer unit stores the received data at the first data rate and transfers the stored data to the parallel port device at the second data rate.Type: GrantFiled: August 4, 1998Date of Patent: July 3, 2001Assignee: Intel CorporationInventors: David G. Ellis, Gene A. Frederiksen, Peter B. Bloch
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Patent number: 6191713Abstract: The present invention is directed to a method and apparatus for converting between serial bus cycles and parallel port commands. A serial bus processor processes a serial bus transaction which is represented by the serial bus cycles and is responsive to the parallel port commands. A state machine circuit is coupled to the serial bus processor to provide a plurality of states corresponding to the serial bus transaction. The state machine circuit transitions from one of the states to any one of the states in response to a change condition asserted by a state signal.Type: GrantFiled: August 4, 1998Date of Patent: February 20, 2001Assignee: Intel CorporationInventors: David G. Ellis, Gene A. Frederiksen
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Patent number: 6119195Abstract: The present invention is a method and apparatus for virtualizing a serial bus information source/sink point of a serial bus device into an address space of a processor. A register unit is coupled to a parallel port device to support a serial bus transaction between the processor and the serial bus device. The register unit has a plurality of registers which are mapped into the address space of the processor via the parallel port device. One of the plurality of registers corresponding to the serial bus information source/sink point. A control circuit is coupled to the register unit to allow the processor to access the information source/sink point via the parallel port device.Type: GrantFiled: August 4, 1998Date of Patent: September 12, 2000Assignee: Intel CorporationInventors: David G. Ellis, Gene A. Frederiksen
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Patent number: 5658200Abstract: A reversing Gravity Fed Orbital Ride "GFOR" (10) produces a repeating, descending and ascending orbital rotation, influenced by the tug of gravity. A plurality of variably inclining and declining paths, defined in a central column (12). A passenger carriage (14) supports seats (48) and guides (22), that interlock with the closed loop paths. Passengers are elevated to an Event Horizon (42) by rotating column (12), while simultaneously inhibiting the rotation of carriage (14). Passengers are driven along a descending orbital course, after reaching the Event Horizon. Thus, passengers can experience an intense centrifugal G-Force sensation and/or weightlessness. When maximum rotational velocity is obtained, a reverse in the vertical direction sends the passengers in an orbital ascent, that slows to a brief stop, reverses it's rotational direction and begins another descent. This repeats until built momentum is spent.Type: GrantFiled: September 18, 1995Date of Patent: August 19, 1997Inventor: David G. Ellis
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Patent number: 5579349Abstract: A number of detection circuits, one for each source of control signal set inputs, and a high speed resolution circuit, are provided for resolving multiple control signal inputs into a single stable, predictable, and useful output signal. The detection circuits detect active control signals in the various control signal set inputs, and generate detected signals. The high speed state resolution circuit generates an output signal, conditionally changing the output state based on the detected signals and the current state being output. When deciding whether to change the output state, the high speed resolution circuit considers only the detected signals applicable to the current output state and responds accordingly, ignoring all other detected signals that are not applicable. The detection circuits and the resolution circuit are coordinated in timings, ensuring proper resolution.Type: GrantFiled: June 30, 1993Date of Patent: November 26, 1996Assignee: Intel CorporationInventors: Gary W. Brady, David G. Ellis
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Patent number: 5548621Abstract: A number of detection circuits, one for each source of control signal set inputs, and a high speed resolution circuit, are provided for resolving multiple control signal inputs into a single stable, predictable, and useful output signal. The detection circuits detect active control signals in the various control signal set inputs, and generate detected signals. The high speed state resolution circuit generates an output signal, conditionally changing the output state based on the detected signals and the current state being output. When deciding whether to change the output state, the high speed resolution circuit considers only the detected signals applicable to the current output state and responds accordingly, ignoring all other detected signals that are not applicable. The detection circuits and the resolution circuit are coordinated in timings, ensuring proper resolution.Type: GrantFiled: December 13, 1994Date of Patent: August 20, 1996Assignee: INTEL CorporationInventors: Gary W. Brady, David G. Ellis
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Patent number: 4457203Abstract: A sound signal automatic detector used in a system with a micro computer and display for automatically detecting an input sound wave, computing from the detected sound wave the fundamental frequency of the sound and displaying its value in a number of different formats. The sound signal detector requires no attention on the part of a musician or other user while it is in operation and comprises a sound signal transducer supplying an amplifier having audio frequency bandpass characteristics compatible with the sound signal frequency spectrum over which sound signals to be analyzed extend. The bandpass characteristics of the amplifier preferably are defined by a high pass filter stage followed by an automatic gain control amplifier that in turn is followed by two stages of low pass filtering.Type: GrantFiled: March 9, 1982Date of Patent: July 3, 1984Assignee: Wright-Malta CorporationInventors: Steve A. Schoenberg, David G. Ellis, Jesse Aronstein
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Reinforcement product for use in cement boards and a method of manufacturing said product and boards
Patent number: 4436564Abstract: The present invention discloses a reinforcement product for use in cement boards and a method of manufacturing said product and of manufacturing cement boards using this product.The reinforcement product of the present invention comprises cross-layered webs of plastic fibres with a preponderance of fibres laid in the trans-axial direction, and continuous filaments or fibrillated tapes located between the layers to impart a high degree of strength in the axial direction. The cross-layered web and the filaments or tapes are compacted to form a reinforcement product which can be rolled up and handled for further processing on cement board forming machines. The webs of plastic fibre are formed by monoaxially orientating on extruded sheet of plastics material in axial direction, then fibrillating the sheet to form a cohesive fibre mass which is cut into lengths and carded to break up the film into a coarse fibrous mass which when stripped from the carding machine forms said plastic fibre web.Type: GrantFiled: August 3, 1981Date of Patent: March 13, 1984Assignee: Plasticisers LimitedInventors: Ian D. Slack, David G. Ellis, Colin Firth -
Patent number: 4421800Abstract: Apparatus for spraying at least one finishing substance onto a material (such as leather) passing a plurality of spray booths having sprayer devices associated therewith. Various inputs relating to (a) sprayer device position, (b) the location and area of material on a moving conveyor carrying the material, (c) conveyor movement, and (d) other related inputs are directed to a single computer unit which communicates command signals which effect the closing of selected normally open valves corresponding to respective sprayer devices. The apparatus provides for limited overspray, accounts for delay following a computer command signal due to valve response time, and include various corrections related to embodiments having sprayer devices which move in nonrectilinear paths. A rotary transformer coupling for improving communication between the computer unit and the valves is provided in rotating sprayer arrangements which have a plurality of sprayer devices, each of which follows a circular path.Type: GrantFiled: February 2, 1982Date of Patent: December 20, 1983Assignee: Digitronics Inventionering Corp.Inventors: Steve Schoenberg, David G. Ellis
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Patent number: 4373981Abstract: The invention relates to a process for the manufacture of objects from water-hardened materials, reinforced with one or more reticulate webs, one over the other, which webs have been obtained by stretching, fibrillating and spreading of a film of organic polymeric material, by continuously supplying one or more reticulate webs, contacting them with a water-hardening material and water, thus forming a composite material, and shaping and hardening this material. This is obtained according the invention in that:a. one or more reticulate webs, one on top of the other, are continuously supplied and laid on a carrier;b. the reticulate webs are folded zig-zag on this carrier;c. the folded network is continuously transported in a direction virtually normal to the direction in which the reticulate webs are supplied;d. subsequently, the folded network is contacted, directly or indirectly, with a water-hardening material and water.Type: GrantFiled: December 18, 1980Date of Patent: February 15, 1983Assignee: Plasticisers, Ltd.Inventors: Joseph J. P. Bomers, David G. Ellis, Johann J. Jansen, Jan M. J. M. Bijen