Patents by Inventor David Harriman

David Harriman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9088495
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 21, 2015
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Patent number: 9071528
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 30, 2015
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Publication number: 20150178241
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 25, 2015
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Patent number: 9049125
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Publication number: 20150078401
    Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type.
    Type: Application
    Filed: December 30, 2013
    Publication date: March 19, 2015
    Inventor: David Harriman
  • Publication number: 20150082091
    Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type.
    Type: Application
    Filed: December 30, 2013
    Publication date: March 19, 2015
    Applicant: Intel Corporation
    Inventor: David Harriman
  • Publication number: 20140304448
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: December 30, 2013
    Publication date: October 9, 2014
    Applicant: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Patent number: 8819306
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 26, 2014
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Patent number: 8793404
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 29, 2014
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Publication number: 20140185436
    Abstract: A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a flow control signal over a link of an interconnect, the flow control signal indicating flow control credits allocated for the device on the channel. The flow control logic is further to update the value of flow control credits based on activity of the device on the channel.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 3, 2014
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David M. Lee
  • Publication number: 20140189174
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 3, 2014
    Applicant: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Publication number: 20140129747
    Abstract: A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.
    Type: Application
    Filed: December 31, 2013
    Publication date: May 8, 2014
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David M. Lee
  • Publication number: 20140112353
    Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Inventor: David Harriman
  • Publication number: 20140115391
    Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Inventor: David Harriman
  • Publication number: 20140115219
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Publication number: 20140105228
    Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Inventor: David Harriman
  • Publication number: 20140105108
    Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Inventor: David Harriman
  • Patent number: 8676362
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for encapsulation of high definition audio data over an input/output interconnect. In some embodiments, a system includes tunneling logic coupled with a high definition (HD) audio controller. The tunneling logic may receive digital audio data from the HD audio controller, encapsulate the digital audio data in a message suitable for an in-band input/output (IO) interconnect, and send the message to an add-in graphics card via the in-band input/output IO interconnect. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: March 18, 2014
    Assignee: Intel Corporation
    Inventors: Douglas Gabel, David Harriman
  • Patent number: 8582602
    Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: November 12, 2013
    Assignee: Intel Corporation
    Inventor: David Harriman
  • Patent number: 8566473
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method for an enhanced general input/output communication architecture includes initializing a flow control mechanism within an general input/output (GIO) interface associated with a virtual channel upon initialization of the virtual channel, and tracking receive buffer availability in a remote GIO interface coupled with the GIO interface by the virtual channel by monitoring an indication associated with an amount of content transmitted from the GIO interface to the remote GIO interface.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: October 22, 2013
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David M. Lee