Abstract: A multi-axis mixing apparatus includes a first motor and a frame supporting the first motor, the first motor configured to selectively rotate a first rotatable assembly about a first axis. The apparatus also includes a second rotatable assembly rotatably supported by the first rotatable assembly, where the second rotatable assembly is rotatable about a second axis. The second rotatable assembly includes a clamping mechanism configured to receive and hold a container containing contents to be mixed, where when the first motor causes the first rotatable assembly to rotate about the first axis, the rotation of the first rotatable assembly about the first axis causes the second rotatable assembly to rotate about the second axis, and where the second axis is substantially perpendicular to the first axis.

Abstract: A self-balancing adapter for use with a mixer, the adapter having a body configured to interface with the mixer as a unit, the body having a front and a back, left and right edges, a top and a bottom, and a vertical axis passing through the top and the bottom, where the front has at least a first recess configured to receive and hold a first vessel substantially within the body; and the adapter having at least one movable counterweight configured to be displaced when the first vessel is received in the first recess such that the movable weight at least partially offsets a weight of the first vessel within the body with respect to the vertical axis.

Abstract: Example implementations relate to system and method of managing transitioning of a computing system to a power-on state from a standby-power state. The computing system includes a manageability controller, an initialization controller, an auxiliary device, and a processor. In such examples, the manageability controller may first determine an initialization status of the auxiliary device from a data corresponding to the auxiliary device, when the computing system is transitioning from the standby-power state to the power-on state. In one or more examples, the initialization status may include the auxiliary device in an initialized stage or a non-initialized stage. Later, the manageability controller may direct the initialization controller to delay the transitioning of the computing system from the standby-power state to the power-on state, in response to determining that the initialization status of the auxiliary device is in the non-initialized stage.

Abstract: An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

Abstract: An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

Abstract: An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

Abstract: An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

Abstract: Disclosed herein are methods and systems for configuring and using one or more block ciphering techniques in order to encrypt/decrypt serial data streams while maintaining cryptographic synchronization and attempting to minimize the amount of overhead introduced into the stream. The techniques disclosed herein may be used to encrypt and decrypt serial data streams using a block cipher in a manner that can be substantially transparent to the devices involved in the serial communication session. For example, the serial user data may be left unframed by the encryption device while monitoring for opportunistic times to transmit framed cryptographic synchronization information during periods of relative inactivity in an asynchronous serial data stream. A cryptographic device implementing the techniques described herein may be configured to implement one or more of an encryption device or a decryption device.

Abstract: Disclosed herein are methods and systems for configuring and using one or more block ciphering techniques in order to encrypt/decrypt serial data streams while maintaining cryptographic synchronization and attempting to minimize the amount of overhead introduced into the stream. The techniques disclosed herein may be used to encrypt and decrypt serial data streams using a block cipher in a manner that can be substantially transparent to the devices involved in the serial communication session. For example, the serial user data may be left unframed by the encryption device while monitoring for opportunistic times to transmit framed cryptographic synchronization information during periods of relative inactivity in an asynchronous serial data stream. A cryptographic device implementing the techniques described herein may be configured to implement one or more of an encryption device or a decryption device.

Abstract: The present invention relates to providing a secure computing environment in a remote server management controller. The exemplary embodiment includes a hierarchy of register security levels restricting register access by communications interfaces shared by the remote server management controller and a managed server associated therewith. Failsafe protection is provided to override register security under certain conditions.

Abstract: A first firmware image is copied from a first memory to a second memory. Firmware access requests are directed from a host processing system to a memory location in the second memory. A second firmware image is written to the first memory. Conditioned on occurrence of a switching event a switch is set to direct firmware access requests from the host processing system to a memory location in the first memory storing the second firmware image. In some cases, firmware access requests are directed from a host processing system to a memory location in a first memory storing a first firmware image. A second firmware image is written to a second memory. Conditioned on occurrence of a switching event, a switch is set to direct firmware access requests from the host processing system to a memory location in the second memory storing the second firmware image.

Abstract: The present invention provides novel anti-infectives that act on Staphylococcus aureus (S. aureus) iron-regulated surface determinants, IsdA, IsdB, IsdC, IsdH (or HarA).

Abstract: Screening methods for identifying compounds that inhibit the SirABC iron-siderophore transport system.

Abstract: The present invention relates to providing a secure computing environment in a remote server management controller. The exemplary embodiment includes a hierarchy of register security levels restricting register access by communications interfaces shared by the remote server management controller and a managed server associated therewith. Failsafe protection is provided to override register security under certain conditions.

Abstract: The present invention relates to providing a secure computing environment in a remote server management controller. The exemplary embodiment includes a hierarchy of register security levels restricting register access by communications interfaces shared by the remote server management controller and a managed server associated therewith. Failsafe protection is provided to override register security under certain conditions.

Abstract: The disclosed embodiments relate to the field of remote server management. More particularly, the embodiments relate to providing an embedded JTAG master in a remote server management controller. In an exemplary embodiment, the JTAG master is adapted to perform command and control functions on a wide range of integrated circuit components within a managed server. The JTAG master may also be configured to provide communication according to the In-Target Probe (ITP) and In-Circuit Emulation (ICE) test methodologies.

Abstract: A remote management controller may include a capture engine and a processor. The capture engine may be configured to: obtain a slice of video data output from a video graphics controller; calculate at least one value correlative to the slice of video data; determine whether any portion of the slice has been locked; and if any portion has not been locked and if the calculated value for such portion of the slice differs from a value for a previously obtained corresponding portion, move the portion to a virtual screen buffer, update a table associated with the virtual screen buffer with the calculated value, and modify a change table to indicate that the portion has changed.

Abstract: A remote management controller may include a video redirection device and a processor. The video redirection device may be configured to: obtain multiple separate slices of video data output from a video graphics controller; calculate at least one value correlative to each of the multiple separate slices of video data; and if the calculated value for any portion of any of the multiple separate slices differs from a value for a previously obtained corresponding portion, update a table associated with an image related to a remote system with the calculated value, process the portion of the slice into a network packet, and move the network packet to one of multiple network buffers. The processor may be configured to: allocate the multiple network buffers; and facilitate transmission of the network packets loaded into the network buffers to the remote system.

Abstract: A remote management controller may include a video redirection device and a processor. The video redirection device may be configured to: obtain a slice of video data output from a video graphics controller; calculate at least one value correlative to the slice of video data; and if the calculated value for any portion of the slice differs from a value for a previously obtained corresponding portion, update a table associated with an image related to a remote system with the calculated value, and process the portion of the slice to create a data portion of a network packet in a network buffer. The processor may be configured to: allocate the network buffer; and provide a header portion of the network packet to the network buffer.

Abstract: A remote management controller may include a capture engine and a processor. The capture engine may be configured to obtain a slice of video data output from a video graphics controller, store the slice of video data, and calculate at least one value correlative to the slice of video data. The processor may be configured to retrieve the slice of video data stored by the capture engine and process any changed portion of the slice of video data for transmission to a remote system.