Abstract: A remote management controller may include a capture engine and a processor. The capture engine may be configured to obtain a slice of video data output from a video graphics controller, calculate at least one value correlative to the slice of video data, and, if the calculated value for any portion of the slice differs from a value for a previously obtained corresponding portion, move the portion to a virtual screen buffer and update a first table associated with the virtual screen buffer with the calculated value, the first table configured to store values for each slice of video data.

Abstract: A system includes proxy logic which detects situations which, unless action is taken, would result in undesirable bus behavior. In one embodiment, the target device of a bus cycle includes proxy logic which determines when the target device is unable to respond correctly to a bus cycle. In this situation, the proxy logic blocks a bus signal from being received by the addressed logic in the target device, thereby preventing the target device from responding at all. In another embodiment, proxy logic is located external to the target device and determines when the target device has not responded to a cycle intended for it. When this condition has occurred, the proxy logic responds to the cycle before the bus's subtractive decode agent has a chance to claim the cycle. The proxy logic's response may be to return bogus data or terminate or abort the cycle.

Abstract: Described are a novel gene (waaP) and a protein (WaaP) which has an enzymatic activity that is involved in heptose modification in the lipopolysaccharide of bacterial membranes. Also described is a method and series of compounds which are active against bacterial pathogens wherein the method comprises the administration of sufficient amount of an inhibitor of WaaP protein activity in gram negative bacteria.

Abstract: The present invention relates to providing a secure computing environment in a remote server management controller. The exemplary embodiment includes a hierarchy of register security levels restricting register access by communications interfaces shared by the remote server management controller and a managed server associated therewith. Failsafe protection is provided to override register security under certain conditions.

Abstract: The disclosed embodiments relate to the field of remote server management. More particularly, the embodiments relate to providing an embedded JTAG master in a remote server management controller. In an exemplary embodiment, the JTAG master is adapted to perform command and control functions on a wide range of integrated circuit components within a managed server. The JTAG master may also be configured to provide communication according to the In-Target Probe (ITP) and In-Circuit Emulation (ICE) test methodologies.

Abstract: The disclosure relates to a remote server management controller that is adapted to be incorporated into a managed server. The disclosed embodiments allow a remote user to communicate with the managed server using out-of-band management communications that are not dependent on the OS of the managed server. The user may obtain management data from the OS or perform other functions remotely by causing the managed server to redirect data from its local communications interfaces to communications interfaces that are available to the remote user.

Abstract: An apparatus controls a signal that indicates to a plug-in component board that it is to be connected to a 64-bit data path in a computer system. The apparatus comprises a timing circuit for receiving a reset signal and providing first and second complementary logical signals in response thereto. A selection switch receives the first and second logical signals as well as a control signal and outputs a third signal as determined by the logical level of the reset signal. A method involves generating first and second complementary signals from a reset signal, selecting between the first complementary signal and a control signal, and outputting a third signal, the logical value of the third signal being determined by the logical value of at least one of the reset signal and the control signal.