Abstract: A system includes an interface and a controller. The interface is configured to receive a state of a substrate processing tool comprising a plurality of process modules configured to process a substrate. The controller is configured to correlate the state with an input previously received by the substrate processing tool from the interface based on the state and to generate an output to control the substrate processing tool based on the correlation.

Abstract: A system includes an interface and a controller. The interface is configured to receive a state a substrate processing tool comprising a plurality of process modules configured to process a substrate. The controller is configured to correlate the state with an input previously received by the substrate processing tool from the interface based on the state and to generate an output to control the substrate processing tool based on the correlation.

Abstract: A cluster architecture and methods for processing a substrate are disclosed. The cluster architecture includes a lab-ambient controlled transfer module that is coupled to one or more wet substrate processing modules. The lab-ambient controlled transfer module and the one or more wet substrate processing modules are configured to manage a first ambient environment. A vacuum transfer module that is coupled to the lab-ambient controlled transfer module and one or more plasma processing modules is also provided. The vacuum transfer module and the one or more plasma processing modules are configured to manage a second ambient environment. And, a controlled ambient transfer module that is coupled to the vacuum transfer module and one or more ambient processing modules is also included. The controlled ambient transfer module and the one or more ambient processing modules are configured to manage a third ambient environment.

Abstract: Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.

Abstract: A vacuum plasma processor includes a roof structure including a dielectric window carrying (1) a semiconductor plate having a high electric conductivity so it functions as an electrode, (2) a hollow coil and (3) at least one electric shield. The shield, coil and semiconductor plate are positioned to prevent substantial coil generated electric field components from being incident on the semiconductor plate. During a first interval the coil produces an RF electromagnetic field that results in a plasma that strips photoresist from a semiconductor wafer. During a second interval the semiconductor plate and another electrode produce an RF electromagnetic field that results in a plasma that etches electric layers, underlayers and photoresist layers from the wafer.

Abstract: A method for processing a substrate is provided which includes generating a meniscus on the surface of the substrate and applying photolithography light through the meniscus to enable photolithography processing of a surface of the substrate.

Abstract: Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.

Abstract: A method for processing a substrate is provided which includes generating a meniscus on the surface of the substrate and applying photolithography light through the meniscus to enable photolithography processing of a surface of the substrate.

Abstract: Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.

Abstract: A method for processing a substrate is provided which includes generating a meniscus on the surface of the substrate and applying photolithography light through the meniscus to enable photolithography processing of a surface of the substrate.

Abstract: A cluster architecture and methods for processing a substrate are disclosed. The cluster architecture includes a lab-ambient controlled transfer module that is coupled to one or more wet substrate processing modules. The lab-ambient controlled transfer module and the one or more wet substrate processing modules are configured to manage a first ambient environment. A vacuum transfer module that is coupled to the lab-ambient controlled transfer module and one or more plasma processing modules is also provided. The vacuum transfer module and the one or more plasma processing modules are configured to manage a second ambient environment. And, a controlled ambient transfer module that is coupled to the vacuum transfer module and one or more ambient processing modules is also included. The controlled ambient transfer module and the one or more ambient processing modules are configured to manage a third ambient environment.

Abstract: A method for filling a trench of a substrate in a controlled environment is provided. The method initiates with etching a trench in the substrate in a first chamber of a cluster tool. A barrier layer configured to prevent electromigration is deposited over an exposed surface of the trench in a second chamber of the cluster tool and the trench is filled with a gap fill material deposited directly onto the barrier layer in the cluster tool. A semiconductor device fabricated by the method is also provided.

Abstract: A semiconductor processing system is provided. The semiconductor processing system includes a first sensor configured to isolate and measure a film thickness signal portion for a wafer having a film disposed over a substrate. A second sensor is configured to detect a film thickness dependent signal in situ during processing, i.e. under real process conditions and in real time. A controller configured to receive a signal from the first sensor and a signal from the second sensor. The controller is capable of determining a calibration coefficient from data represented by the signal from the first sensor. The controller is capable of applying the calibration coefficient to the data associated with the second sensor, wherein the calibration coefficient substantially eliminates inaccuracies introduced to the film thickness dependent signal from the substrate. A method for calibrating an eddy current sensor is also provided.

Abstract: A vacuum plasma processor includes a roof structure including a dielectric window carrying (1) a semiconductor plate having a high electric conductivity so it functions as an electrode, (2) a hollow coil and (3) at least one electric shield. The shield, coil and semiconductor plate are positioned to prevent substantial coil generated electric field components from being incident on the semiconductor plate. During a first interval the coil produces an RF electromagnetic field that results in a plasma that strips photoresist from a semiconductor wafer. During a second interval the semiconductor plate and another electrode produce an RF electromagnetic field that results in a plasma that etches electric layers, underlayers and photoresist layers from the wafer.

Abstract: A first proximity head is configured to define a meniscus of a photoresist developer solution on a substrate. The meniscus is to be defined between a bottom of the first proximity head and the substrate. A second proximity head is configured to define a rinsing meniscus on the substrate and remove the rinsing meniscus from the substrate. The second proximity head is positioned to follow the first proximity head relative to a traversal direction of the first and second proximity heads over the substrate. Exposure of the substrate to the meniscus of photoresist developer solution causes previously irradiated photoresist material on the substrate to be developed to render a patterned photoresist layer. The first and second proximity heads enable precise control of a residence time of the photoresist developer solution on the substrate during the development process.

Abstract: A vacuum plasma processor includes a roof structure including a dielectric window carrying (1) a semiconductor plate having a high electric conductivity so it functions as an electrode, (2) a hollow coil and (3) at least one electric shield. The shield, coil and semiconductor plate are positioned to prevent substantial coil generated electric field components from being incident on the semiconductor plate. During a first interval the coil produces an RF electromagnetic field that results in a plasma that strips photoresist from a semiconductor wafer. During a second interval the semiconductor plate and another electrode produce an RF electromagnetic field that results in a plasma that etches electric layers, underlayers and photoresist layers from the wafer.

Abstract: A method and an apparatus for enhancement of the for measuring resistance-based features of a substrate is provided. The apparatus includes a sensor configured to detect a signal produced by a eddy current generated electromagnetic field. The magnetic field enhancing source is positioned to the alternative side of the object under measurement relative to the sensor to enable the sensitivity enhancing action. The sensitivity enhancing source increases the intensity of the eddy current generated in the object under measurement, and as a result the sensitivity of the sensor. A system enabled to determine a thickness of a layer and a method for determining a resistance-based feature characteristic are also provided.

Abstract: A method for converting a slope based detection task to a threshold based detection task is provided. The method initiates with defining an approximation equation for a set of points corresponding to values of a process being monitored. Then, an expected value at a current point of the process being monitored is predicted. Next, a difference between a measured value at the current point of the process being monitored and the corresponding expected value is calculated. Then, the difference is monitored for successive points to detect a deviation value between the measured value and the expected value. Next, a transition point for the process being monitored is identified based on the detection of the deviation value. A processing system configured to provide real time data for a slope based transition and a computer readable media are also provided.

Abstract: A plasma processing system for processing a substrate, is disclosed. The plasma processing system includes a single chamber, substantially azimuthally symmetric plasma processing chamber within which a plasma is both ignited and sustained for the processing. The plasma processing chamber has no separate plasma generation chamber. The plasma processing chamber has an upper end and a lower end. The plasma processing chamber includes a material that does not substantially react with the reactive gas chemistries that are delivered into the plasma processing chamber. In addition, the reactant gases that are flown into the plasma processing chamber are disclosed.

Abstract: A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded in the wafer carrier. The sensor is configured to induce an eddy current in the wafer to determine a proximity and a thickness of the wafer. A sensor array external to the CMP tool is included. The sensor array is in communication with the sensor embedded in the wafer carrier and substantially eliminates a distance sensitivity. The sensor array provides an initial thickness of the wafer to allow for a calibration to be performed on the sensor embedded in the wafer carrier. The calibration offsets variables causing inaccuracies in the determination of the thickness of the wafer during CMP operation. A method and an apparatus are also provided.