Abstract: A pinned interposer and mating sockets to facilitate removable mounting of high connection density micro devices between a pair of substrates in compact electronic circuit packages. The pinned interposer has an inner set of contacts, typically in a rectangular array, that, in cooperation with a mating socket, allows pluggable connection of a micro device such as a MEMS device connected to a first printed circuit substrate. An outer set of contacts on the interposer provides electrical interconnection between the first substrate and a second substrate located atop the high connection density micro device, thereby effectively sandwiching the micro device between the first and second substrates. The outer set of contacts may be disposed in a circular array.

Abstract: A pinned interposer and mating sockets to facilitate removable mounting of high connection density micro devices between a pair of substrates in compact electronic circuit packages. The pinned interposer has an inner set of contacts, typically in a rectangular array, that, in cooperation with a mating socket, allows pluggable connection of a micro device such as a MEMS device connected to a first printed circuit substrate. An outer set of contacts on the interposer provides electrical interconnection between the first substrate and a second substrate located atop the high connection density micro device, thereby effectively sandwiching the micro device between the first and second substrates. The outer set of contacts may be disposed in a circular array.

Abstract: A flexible circuit electronic package including a heat sink, a flexible circuit having a semiconductor chip positioned thereon and electrically coupled thereto, and a quantity of heat shrunk adhesive securing the flexible circuit to the heat sink such that the flexible circuit is planar. This package is then adapted for being positioned on and electrically coupled to a circuitized substrate such as a printed circuit board. A method of making this package is also provided.

Abstract: An electronic package which includes a substrate (e.g., a chip carrier substrate or a PCB), an electronic component (e.g., a semiconductor chip), a heatsink and a thermal interposer for effectively transferring heat from the chip to the heatsink. The interposer includes a compressible, resilient member (e.g., an elastomeric pad) and a plurality of thin, metallic sheets (e.g., copper foils) and the thickness thereof can be adjusted by altering the number of such foils.

Abstract: A flexible circuit electronic package including a heat sink, a flexible circuit having a semiconductor chip positioned thereon and electrically coupled thereto, and a quantity of heat shrunk adhesive securing the flexible circuit to the heat sink such that the flexible circuit is planar. This package is then adapted for being positioned on and electrically coupled to a circuitized substrate such as a printed circuit board. A method of making this package is also provided.

Abstract: A method of making a circuitized substrate (e.g., a chip carrier) with solder balls thereon which are each formed in such a manner so as to have rough surfaces thereon, thereby providing enhanced connections with conductors (e.g., conductive sites) of an electronic device (e.g., a semiconductor chip). Methods of making an electrical assembly including both substrate and device, as well as this assembly and another substrate, thereby forming a multiple substrate assembly, are also provided.

Abstract: A method and structure for forming an electronic structure that comprises a redistribution structure on a circuitized substrate. The redistribution structure includes N dielectric layers (N?2) and N metal planes formed in the following sequence: dielectric layer 1 on a metallic plane that exists on a surface of the substrate, metal plane 1 on dielectric layer 1, dielectric layer 2 on dielectric layer 1 and metal plane 1, metal plane 2 on the dielectric layer 2, . . . , dielectric layer N on dielectric layer N?1 and metal plane N?1, and metal plane N on the dielectric layer N. Metal planes or metallic planes may include signal planes, power planes, ground planes, etc. A microvia structure, which is formed through the N dielectric layers and electrically couples metal plane N to the metallic plane, includes a microvia or a portion of a microvia through each dielectric layer.

Abstract: An electronic package having one or more components comprising: a substrate having a first coefficient of thermal expansion; a lid attached to the substrate, the lid including a vapor chamber, the lid having a second coefficient of thermal expansion, the first coefficient of thermal expansion matched to the second coefficient of expansion; a thermal transfer medium in contact with a back surface of each component and an outer surface of a lower wall of the lid; and each component electrically connected to a top surface of the substrate.

Abstract: An electronic package, such as a chip carrier, with an optimized circuit pattern having a circuitized substrate with a first and second circuit pattern is provided. The circuitized substrate includes a corner surface region. The second circuit pattern is electrically connected to the first circuit pattern on the corner surface region of the circuitized substrate and is positioned in such a manner so as to substantially inhibit cracking of the first circuit pattern during flexure of the chip carrier.

Abstract: An electronic package includes a substrate having a contact pad thereon, a reformable member such as a solder ball positioned on the contact pad, and an elastic member positioned around the reformable member. The elastic member exerts a girdling force on the reformable member so that when the reformable member is softened, the elastic member elongates the reformable member. This elongation accommodates thermal and other stresses between the foregoing substrate and another substrate joined at the free end of the reformable member. An apparatus is also provided for positioning the elastic member on and around the reformable member.

Abstract: An electronic package and method of making same in which a circuitized substrate having a first stiffness includes a plurality of electrically conductive circuit members on a first portion of the circuitized substrate and is adapted for having solder connections thereon and for being electrically connected to a semiconductor chip. A stiffener layer having a second stiffness is positioned on a second portion of the circuitized substrate relative to the first portion, the second stiffness of the stiffener layer distributing a portion of the first stiffness of said circuitized substrate so as to substantially prevent failure of the solder connections between the electrically conductive circuit members and the semiconductor chip during operation of the electronic package.

Abstract: An electronic package includes a substrate having a contact pad thereon, a reformable member such as a solder ball positioned on the contact pad, and an elastic member positioned around the reformable member. The elastic member exerts a girdling force on the reformable member so that when the reformable member is softened, the elastic member elongates the reformable member. This elongation accommodates thermal and other stresses between the foregoing substrate and another substrate joined at the free end of the reformable member. An apparatus is also provided for positioning the elastic member on and around the reformable member.

Abstract: A method and structure to adhesively couple a cover plate to a semiconductor device. A semiconductor device is electrically coupled to a substrate. A stiffener ring surrounding the semiconductor device is adhesively coupled to the substrate. A cover plate is adhesively coupled to both a top surface of the semiconductor device and a top surface of the stiffener ring using a first and second adhesive, respectively. The modulus of the first adhesive is less than the modulus of the second adhesive.

Abstract: A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

Abstract: A method and structure for forming an electronic structure that comprises a redistribution structure on a circuitized substrate. The redistribution structure includes N dielectric layers (N ?2) and N metal planes formed in the following sequence: dielectric layer 1 on a metallic plane that exists on a surface of the substrate, metal plane 1 on dielectric layer 1, dielectric layer 2 on dielectric layer 1 and metal plane 1, metal plane 2 on the dielectric layer 2, . . . , dielectric layer N on dielectric layer N-1 and metal plane N-1, and metal plane N on the dielectric layer N. Metal planes or metallic planes may include signal planes, power planes, ground planes, etc. A microvia structure, which is formed through the N dielectric layers and electrically couples metal plane N to the metallic plane, includes a microvia or a portion of a microvia through each dielectric layer.

Abstract: A stress-relieving heatsink structure and method of forming thereof for an electronic package, for instance, that including a semiconductor chip package which is mounted on a wired carrier, such as a circuitized substrate. The heatsink structure is constituted from a plurality of base structures which are joined along slits so as to impart a degree of flexibility to the electronic package inhibiting the forming of stresses tending to cause delamination of the package components.

Abstract: A circuitized substrate which utilizes an underlying conductive layer coupled to a pad on the substrate to assure a reinforced pad which will not be damaged or removed from the substrate when subjected to a significant load. Two or more pads can be similarly provided and coupled to the conductive layer, e.g., the layer being a common (ground) layer. An information handling system (e.g., a personal computer) utilizing the substrate is also provided.

Abstract: The present invention provides a flexible shear-compliant laminate connector having a plurality of contacts formed on a first surface and second surface of the connector, wherein select contacts on the first surface of the connector are off-set from select contacts on the second surface of the connector.

Abstract: An electronic package, such as a chip carrier, with an optimized circuit pattern having a circuitized substrate with a first and second circuit pattern is provided. The circuitized substrate includes a corner surface region. The second circuit pattern is electrically connected to the first circuit pattern on the corner surface region of the circuitized substrate and is positioned in such a manner so as to substantially inhibit cracking of the first circuit pattern during flexure of the chip carrier.

Abstract: A method and structure to adhesively couple a cover plate to a semiconductor device. A semiconductor device is electrically coupled to a substrate. A stiffener ring surrounding the semiconductor device is adhesively coupled to the substrate. A cover plate is adhesively coupled to both a top surface of the semiconductor device and a top surface of the stiffener ring using a first and second adhesive, respectively. The modulus of the first adhesive is less than the modulus of the second adhesive.