Patents by Inventor David J. Hansen

David J. Hansen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming wafer alignment patterns
    Patent number: 5798292
    Abstract: A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective-series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: August 25, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Jost, David J. Hansen, Steven M. McDonald
  • Process for producing large quantities of viable true seed from garlic
    Patent number: 5746024
    Abstract: Large quantities of true seed is obtained from garlic using a process that involves the growing of a garlic parent plant from a virus-free garlic propagule under virus-free conditions such that the garlic parent plant remains free from virus infection and in particular infection by the onion yellow dwarf virus.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: May 5, 1998
    Assignee: Rogers Foods, Inc.
    Inventors: Robert M. Rice, Kevin B. Brink, David J. Hansen
  • Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns
    Patent number: 5700732
    Abstract: A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: December 23, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Jost, David J. Hansen, Steven M. McDonald