Abstract: In some embodiments, a chip includes transmitters and generation circuitry to provide data symbols and special characters to the transmitters to be transmitted. The chip also includes match detection circuitry to detect when the data symbols match the special characters; and indicator symbol generation circuitry to create data indicator symbols in response to detected matches and to provide the data indicator symbols to the generation circuitry to be provided to the transmitters to be transmitted. Other embodiments are described.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: A method and apparatus for synchronizing time between a master device and a target device arranged across a network, wherein the target device communicates to the master device through a PCIe interconnect includes transmitting a first message at a first time from the master device to the target device, the first message including a message indicator; and receiving a reply message at a subsequent time from the target device to the master device, the reply message including the message indicator.

Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.

Abstract: In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving at a target device a request for a deterministic idle window from an initiator device via an interconnect, determining whether to accept the request, e.g., based on an anticipated time until the target device's next activity, and sending an acknowledgment to the initiator device based on the determination. The initiator and target devices may enter an extended idle state based on the determination. Other embodiments are described and claimed.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed.

Abstract: A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving a communication in a protocol stack coupled to a tunneling interconnect, determining whether a communication type is subject to altered timing to accommodate a delay associated with the tunneling interconnect, adjusting a timing of at least one stack logic to accommodate the delay, and handling the communication using the adjusted timing. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes transmitters and generation circuitry to provide data symbols and special characters to the transmitters to be transmitted. The chip also includes match detection circuitry to detect when the data symbols match the special characters; and indicator symbol generation circuitry to create data indicator symbols in response to detected matches and to provide the data indicator symbols to the generation circuitry to be provided to the transmitters to be transmitted. Other embodiments are described.

Abstract: In one embodiment, the present invention includes an apparatus having an upstream component including a plurality of virtual bridges to control communication with a corresponding plurality of endpoint components coupled downstream of the upstream component and a shared port. The apparatus may further include a first endpoint component coupled to the upstream component via a first link and a second endpoint component coupled to the first endpoint component via a second link and to the upstream component via a third link, where the upstream component and the endpoint components are coupled in a daisy chain topology. Other embodiments are described and claimed.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: A transaction rule is used to recognize a set of simulation signals obtained from a design simulation as a transaction. An action associated with the transaction rule is executed to produce an output identifying the transaction.

Abstract: A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a first agent, a point to point half duplex interface coupled to the first agent and a second agent coupled to the first point to point half duplex interface. The first agent is adaptable to transmit a signal to the second agent via a first component of the interface indicating the type of data traffic to be transmitted to the second agent.

Abstract: According to one embodiment, a computer comprises a central processing unit (CPU), a first hub agent, a first hub interface coupled to the first hub agent, and a second hub agent coupled to the first hub interface. The first and second hub agents operate at a first data clocking rate determined by exchanging data clocking rate capabilities.

Abstract: According to one embodiment, a computer comprises a central processing unit (CPU), a first hub agent, a first hub interface coupled to the first hub agent, and a second hub agent coupled to the first hub interface. The first and second hub agents operate at a first data clocking rate determined by exchanging data clocking rate capabilities.