Abstract: A system and method for ensuring the execution of commands is visible throughout that system. A flush command is received and enqueued in a first queue together with a synchronization value enqueued in a second queue. The flush command is delayed from being dequeued from the first queue until both the flush command and the synchronization value are advanced to the head of their respective queues. Thereafter, the flush command is dequeued subsequently causing the return of a quad-word of random data as an acknowledge signal.

Abstract: In a computer system processing out of order commands, a method for detecting situations in which errors could be caused by execution of an out of order command. The method includes the steps of receiving a first address of a first type and receiving a next address of the first type. Information is accumulated regarding differences between the first address and the next address. The method also includes receiving an address of a second type and using the accumulated information to determine whether the address of the second type is an address associated with a command whose execution can create a hazard. A hazard indication is generated if it is determined that the address of the second type is an address associated with a command whose execution can create a hazard. In one embodiment, the first type of address is an address associated with a first type of command and the second type of address is an address associated with a second type of command.

Abstract: A method and apparatus for transferring data from a first bus to a second bus. A bridge couples a first bus to a second bus. The bridge includes a buffer to store two data elements of a first packet transferred to the buffer from the first bus. The bridge also includes a controller that permits a first data element to be transferred from the buffer to the second bus. In addition, if at least a portion of a second packet has not been transferred to the bridge from the first bus, then the controller causes at least one wait state to be inserted on the second bus before transferring the second data element of the first packet from the buffer to the second bus.

Abstract: A data storage array is provided having a number, n, of sequential data storage areas for the storage of data. A valid status array including n bits is provided where there is a one to one correspondence between the bits of the valid status array and the data storage areas of the data storage array. When valid data are written into a data storage area, the status bit of the valid status array corresponding to this data storage area is set to indicate that valid data are present. When data are read out of the data storage area, the corresponding status bit is cleared indicating the absence of valid data. If the data storage array is one that is written to in a random access manner and read from sequentially, as a queue, then the valid status array would indicate the presence of valid data at the head of the queue for the data storage array.