Abstract: A single terminal is usable to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is tied low by an external connection, or 2) is tied high by an external connection, or 3) is floating or is substantially floating. If the circuit determines that the terminal is floating or is substantially floating, then the circuit sets an operational characteristic of a portion of the circuit (for example, sets a maximum current with which the circuit charges a battery) to have a value that is a function of a resistance of an external resistor coupled to the terminal. If no external resistor is present, then the terminal is floating and the operational characteristic is set to have a zero value. The terminal and circuit are particularly suited to use in a USB battery charger.

Abstract: A driver circuit (for example, in a switching power supply or in a Class-D switching amplifier) drives a gate of a switch during a transition with a low output impedance during an initial period and then for the remainder of the transition drives the gate with a midrange output impedance. The switch in turn switches current flow through an inductor. The driver circuit includes a “Drive Node Voltage Dependent Impedance Circuit” (DNVDIC) that couples the gate to a supply voltage node. In one embodiment, there are two resistive current paths through the DNVDIC. A non-linear device in the first current path switches from having a small to a large impedance when a voltage drop across the device falls below a threshold voltage. The resulting increase in impedance of the first current path decreases voltage edge rates and reduces noise, whereas the low initial impedance reduces transition power losses.

Abstract: An integrated circuit includes a buck converter controller, a PFET, an NFET that is coupled in common drain configuration to the PFET, a first microbump that is connected to the source of the PFET, a second microbump that is connected to the source of the NFET, a third microbump that is connected to the common drain node, a fourth microbump that is connected to a feedback input lead of the controller, and a plurality of other microbumps. The other microbumps are utilized to supply signals to and/or to conduct signals from the controller. A respective one of the four microbumps is disposed to occupy a respective one of the four corners of a square pattern. The other microbumps are disposed in a regular grid along with the four microbumps, but none of the other microbumps is disposed between any two of the four microbumps.

Abstract: A primary-side regulation (PSR) controller integrated circuit includes a PSR CC/CV controller and a non-volatile shift register. An assembled power supply that includes the integrated circuit is in-circuit tested to determine errors in power supply output voltage and/or current. Programming information is determined and shifted into the shift register. During programming, the power supply regulates to a different output voltage, and the different voltage is used for shift register programming. After programming, the power supply operates in a normal mode so that the output voltage and current are within specification. The voltage and current to which the power supply regulates are set by some of the bits of the programming information.

Abstract: A primary-side regulation (PSR) controller integrated circuit includes a PSR CC/CV controller and a non-volatile shift register. An assembled power supply that includes the integrated circuit is in-circuit tested to determine errors in power supply output voltage and/or current. Programming information is determined and shifted into the shift register. During programming, the power supply regulates to a different output voltage, and the different voltage is used for shift register programming. After programming, the power supply operates in a normal mode so that the output voltage and current are within specification. The voltage and current to which the power supply regulates are set by some of the bits of the programming information.

Abstract: A single terminal is usable to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is tied low by an external connection, or 2) is tied high by an external connection, or 3) is floating or is substantially floating. If the circuit determines that the terminal is floating or is substantially floating, then the circuit sets an operational characteristic of a portion of the circuit (for example, sets a maximum current with which the circuit charges a battery) to have a value that is a function of a resistance of an external resistor coupled to the terminal. If no external resistor is present, then the terminal is floating and the operational characteristic is set to have a zero value. The terminal and circuit are particularly suited to use in a USB battery charger.

Abstract: A low-cost integrated circuit is used as a secondary side constant voltage and constant current controller. The integrated circuit has four terminals and two amplifier circuits. A first amplifier circuit is used to sense a voltage on a FB terminal and in response to cause a first current to flow through an OPTO terminal. A second amplifier circuit is used to sense a voltage between a SENSE terminal and a SOURCE terminal and in response to cause a second current to flow through the same OPTO terminal. The FB terminal is used for output voltage feedback and is also used to supply power onto the integrated circuit. The SOURCE terminal is used for output current feedback and is also used as power supply return for the integrated circuit. The cost of the integrated circuit is reduced by having only four terminals.

Abstract: A system involves LED strings and programmable current source circuits (CSC). An LED current flows through each LED string. Each LED current is controlled by an associated programmable CSC. In one embodiment, the CSCs form a chain. A first CSC uses a reference current for calibration, and thereafter supplies the reference current to the next CSC. When the next CSC detects the reference current, it uses the reference current for calibration. CSCs are calibrated one by one down the chain. In a second embodiment, each CSC can receive the reference current from a common conductor. If the common conductor is detected to be available, then the CSC uses the reference current for calibration. When the conductor is in use, the other CSCs detect the conductor as unavailable and do not attempt to self-calibrate. The CSCs use the reference current one by one, but in an order that changes over time.

Abstract: An integrated circuit includes a buck converter controller, a PFET, an NFET that is coupled in common drain configuration to the PFET, a first microbump that is connected to the source of the PFET, a second microbump that is connected to the source of the NFET, a third microbump that is connected to the common drain node, a fourth microbump that is connected to a feedback input lead of the controller, and a plurality of other microbumps. The other microbumps are utilized to supply signals to and/or to conduct signals from the controller. A respective one of the four microbumps is disposed to occupy a respective one of the four corners of a square pattern. The other microbumps are disposed in a regular grid along with the four microbumps, but none of the other microbumps is disposed between any two of the four microbumps.

Abstract: An integrated circuit includes a plurality of tiles. One tile is a master tile. Other tiles contain writable registers of memory structures. Information for configuring circuitry of the tile is stored in the register in the tile. An individual one of the registers can be written via the master tile. Each memory structure of a register includes a non-volatile floating gate cell (that stores the configuration information) as well as a volatile cell. All transistors have the same gate insulator thickness. Although a programming pulse signal is applied to all memory structures, the state of the non-volatile cell of a memory structure is only changed if the state stored by the associated non-volatile cell differs from the state stored by the volatile cell. Floating gates are automatically refreshed by the programming pulse signal. By storing configuration information in each tile, inefficiencies associated with using blocks of non-volatile memory are avoided.

Abstract: The present invention provides an apparatus and method for improving the accuracy of circuits. The apparatus includes a replicate circuit and a trim determination circuit. The trim determination circuit includes a measurable circuit element and determines the state of the measurable element. The replicate circuit includes a replicate circuit element which has similar electrical characteristics as the measurable element, and is configured to aid in determining an adjustable test current. The trim determination circuit generates a test current which is proportional to the adjustable test current. The test current is passed through the measurable element such that a first voltage drop occurs across the measurable element. A measured current is generated at a current level dictated by the voltage drop across the measurable element, such that the state of the measurable element is determined by the difference between the measured current and a scaled reference current.

Abstract: Systems and methods for the measurement of optical power in optical fiber are disclosed. The optical signal is converted to an electrical signal, which is then converted to a digital output code that indicates the relative strength of the optical signal in terms of logarithmic units.

Abstract: The present invention provides an apparatus and method for improving the accuracy of circuits. The apparatus includes a replicate circuit and a trim determination circuit. The trim determination circuit includes a measurable circuit element and determines the state of the measurable element. The replicate circuit includes a replicate circuit element which has similar electrical characteristics as the measurable element, and is configured to aid in determining an adjustable test current. The trim determination circuit generates a test current which is proportional to the adjustable test current. The test current is passed through the measurable element such that a first voltage drop occurs across the measurable element. A measured current is generated at a current level dictated by the voltage drop across the measurable element, such that the state of the measurable element is determined by the difference between the measured current and a scaled reference current.

Abstract: The present invention provides an apparatus and method for improving the accuracy of circuits. The apparatus includes a replicate circuit and a trim determination circuit. The trim determination circuit includes a measurable circuit element and determines the state of the measurable element. The replicate circuit includes a replicate circuit element which has similar electrical characteristics as the measurable element, and is configured to aid in determining an adjustable test current. The trim determination circuit generates a test current which is proportional to the adjustable test current. The test current is passed through the measurable element such that a first voltage drop occurs across the measurable element. A measured current is generated at a current level dictated by the voltage drop across the measurable element, such that the state of the measurable element is determined by the difference between the measured current and a scaled reference current.

Abstract: A stable, reliable, op-amp circuit overcomes the adverse affect of input offset voltages, VOSI, present at the input of op-amp. In one application, such VOSI-compensated op-amps employ a standard bandgap voltage input to achieve an improved voltage regulated reference source. A new circuit combination includes an auto-zero circuit arrangement intermediate an input network and the op-amp exhibiting the input voltage offset. In an auto-zero mode, the new auto-zero circuit arrangement samples the op amp's VOSI and redistributes the sampled signal in a storage network for use in compensating for the VOSI while operating in a normal mode. As the potential for VOSI problems again develops, another auto-zero pulse causes the circuit arrangement to switch again to the auto-zero mode and the cycle continues. Because the auto-zero arrangement employs the actual VOSI encountered in a specific op-amp, and that value for VOSI is used to null the error-causing input, the circuit arrangement is self-calibrating.

Abstract: Current-level monitoring circuitry incorporating a full-time coarse monitor and a part-time fine monitor and capable of generating control signals when the current-level being monitored reaches certain predetermined thresholds. In its preferred embodiment the invention is incorporated into battery-protection circuitry, guarding against both excess charging currents and excess discharging currents. A key concept of the invention is a hierarchical monitoring system incorporating a full-time coarse monitor that activates the fine monitor only when the battery current level enters a certain range and then deactivates it once the level falls out of that range again. Should the current level continue to rise up to the threshold of unsafe battery current, the fine monitor will disconnect the battery. In the preferred embodiment of the invention, the fine monitor operates by comparing, with a predetermined reference voltage, the voltage drop across a fine sensing resistor through which battery current is directed.

Abstract: In a temperature measuring circuit suitable for implementation on an integrated circuit (IC) a plurality, M, nominally unit value current sources are individually and collectively applied to a sensor such as a diode or transistor. The resulting individual V.sub.BE voltages are measured and used to form an average, V.sub.BE(AVG), of the individual voltages. The difference .DELTA.V.sub.BE between the voltage, V.sub.BE(TOT), resulting from application of all M current sources and V.sub.BE(AVG) is used to solve for temperature in a relationship that is independent of the current values used. An error-corrected version of a sigma-delta analog-to-digital converter (ADC) is used to convert the analog measurements into digital signals representative of temperature.

Abstract: A leadframe for sensing electrical parameters in an integrated circuit package includes an interconnect pattern having a plurality of patterned conductive pads connected to a plurality of leads for connecting to an integrated circuit and a resistor which is integral with the leadframe and connects selected conductive pads to form a resistive connection between two of the leads.

Abstract: A complementary transistor class AB output stage (200) utilizes a complementary pair of output drivers (220, 222) connected in series between the power supply rails (210, 216) to furnish the stage output. An output driver (206) is a composite pair of transistors in a Darlington configuration, which boosts the current gain and input resistance of the output stage. Bases of the output drivers are connected by a complementary pair of parallel connected drivers (226, 228), which function as common base level shifters. Quiescent bias of the output drivers is achieved by a pair of constant current transistors (232, 238) that are operated as complementary current mirrors. Inputs to the mirrors are relatively low current sink (252) and source (250) supplies.

Abstract: A track-and-hold circuit that consists of an operational amplifer wherein the same capacitors are used for phase compensation and as differential holding capacitors. The circuit is switched from track to hold by turning off the input stage by reverse biasing base-emitter junctions through current steering in combination with resistor clamping. Low impedance during the hold mode is maintained because one half of the differential compensation path is connected to the output. Feed-through is eliminated by cascoding the first stage and turning off the cascode devices through current steering with resistor clamping during the holding mode. The holding capacitors' droop due to bias currents is minimized by current cancellation of the second stage.