Patents by Inventor David J. Llapitan
David J. Llapitan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10211120Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.Type: GrantFiled: December 23, 2015Date of Patent: February 19, 2019Assignee: Intel CorporationInventors: Russell S. Aoki, Jonathan W. Thibado, Jeffory L. Smalley, David J. Llapitan, Thomas A. Boyd, Harvey R. Kofstad, Dimitrios Ziakas, Hongfei Yan
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Publication number: 20180007791Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.Type: ApplicationFiled: September 12, 2017Publication date: January 4, 2018Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
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Patent number: 9848510Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.Type: GrantFiled: December 19, 2014Date of Patent: December 19, 2017Assignee: Intel CorporationInventors: Vijaykumar Krithivasan, Jeffory L. Smalley, David J. Llapitan, Gaurav Chawla, Mani Prakash, Susan F. Smith
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Patent number: 9832876Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.Type: GrantFiled: December 18, 2014Date of Patent: November 28, 2017Assignee: Intel CorporationInventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
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Publication number: 20170186661Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.Type: ApplicationFiled: December 23, 2015Publication date: June 29, 2017Inventors: Russell S. Aoki, Jonathan W. Thibado, Jeffory L. Smalley, David J. Llapitan, Thomas A. Boyd, Harvey R. Kofstad, Dimitrios Ziakas, Hongfei Yan
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Patent number: 9681556Abstract: In one embodiment, a load frame and an integrated circuit device are aligned, with a base frame carried on a substrate, along a first alignment axis defined by a first alignment post extending from the base frame to the load frame, in a direction transverse to the substrate, and a first biasing device carried on the base frame is actuated to engage and bias the load frame toward the base frame aligned with the load frame, and to bias the integrated circuit toward the substrate. A latch latches the load and base frames together, aligned with and biased towards each other with the integrated circuit device and the substrate aligned with, and biased toward each other. Other aspects and features are also described.Type: GrantFiled: September 28, 2012Date of Patent: June 13, 2017Assignee: INTEL CORPORATIONInventors: David J. Llapitan, Neal E. Ulen, Jeffory L. Smalley
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Patent number: 9603276Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.Type: GrantFiled: December 26, 2014Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado, Kuang Liu, Gregorio Murtagian
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Patent number: 9490560Abstract: A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.Type: GrantFiled: December 19, 2014Date of Patent: November 8, 2016Assignee: Intel CorporationInventors: Gaurav Chawla, David J. Llapitan, Jeffory L. Smalley, Tejinder Pal Aulakh, Vijaykumar Krithivasan, Donald T. Tran
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Patent number: 9385457Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.Type: GrantFiled: December 8, 2014Date of Patent: July 5, 2016Assignee: Intel CorporationInventors: Gaurav Chawla, Joshua D Heppner, Zhichao Zhang, David J. Llapitan, Vijaykumar Krithivasan
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Publication number: 20160190716Abstract: Some forms relate to a socket having a housing. A first receiving pin field is formed as part of the housing. The first pin receiving field includes a first plurality of electrical contacts. A second receiving pin field is formed as part of the housing. The second pin field includes a second plurality of electrical contacts. An actuation mechanism is configured to engage the first plurality electrical contacts with a first set of pins on a first electronic package and the second plurality electrical contacts with a second set of pins on a second electronic package.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: Kuang Liu, Gregorio Murtagian, David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado
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Publication number: 20160190717Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: David J. Llapitan, Jeffory L. Smalley, Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Jonathan W. Thibado, Kuang Liu, Gregorio Murtagian
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Publication number: 20160181714Abstract: A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: GAURAV CHAWLA, David J. Llapitan, Jeffory L. Smalley, Tejinder Pal Aulakh, Vijaykumar Krithivasan, Donald T. Tran
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Publication number: 20160183374Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.Type: ApplicationFiled: December 18, 2014Publication date: June 23, 2016Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
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Publication number: 20160183375Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Vijaykumar Krithivasan, Jeffory L. Smalley, David J. Llapitan, Gaurav Chawla, Mani Prakash, Susan F. Smith
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Patent number: 9265170Abstract: Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.Type: GrantFiled: October 28, 2013Date of Patent: February 16, 2016Assignee: Intel CorporationInventors: Rajasekaran Swaminathan, Ram S. Viswanath, Sanka Ganesan, Gaurav Chawla, Joshua D. Heppner, Jeffory L. Smalley, Vijaykumar Krithivasan, David J. Llapitan, Neal E. Ulen, Donald T. Tran
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Publication number: 20150249298Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.Type: ApplicationFiled: December 8, 2014Publication date: September 3, 2015Inventors: Gaurav Chawla, Joshua D. Heppner, Zhichao Zhang, David J. Llapitan, Vijaykumar Krithivasan
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Publication number: 20150118870Abstract: Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: October 28, 2013Publication date: April 30, 2015Inventors: Rajasekaran Swaminathan, Ram S. Viswanath, Sanka Ganesan, Gaurav Chawla, Joshua D. Heppner, Jeffory L. Smalley, Vijaykumar Krithivasan, David J. Llapitan, Neal E. Ulen, Donald T. Tran
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Patent number: 8905794Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.Type: GrantFiled: December 11, 2012Date of Patent: December 9, 2014Assignee: Intel CorporationInventors: Gaurav Chawla, Joshua D Heppner, Zhichao Zhang, David J. Llapitan, Vijaykumar Krithivasan
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Publication number: 20140162475Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Inventors: Gaurav Chawla, Joshua D. Heppner, Zhichao Zhang, David J. Llapitan, Vijaykumar Krithivasan
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Publication number: 20140092573Abstract: In one embodiment, a load frame and an integrated circuit device are aligned, with a base frame carried on a substrate, along a first alignment axis defined by a first alignment post extending from the base frame to the load frame, in a direction transverse to the substrate, and a first biasing device carried on the base frame is actuated to engage and bias the load frame toward the base frame aligned with the load frame, and to bias the integrated circuit toward the substrate. A latch latches the load and base frames together, aligned with and biased towards each other with the integrated circuit device and the substrate aligned with, and biased toward each other. Other aspects and features are also described.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: David J. LLAPITAN, Neal E. ULEN, Jeffory L. SMALLEY