Abstract: Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of gates disposed on the quantum well stack; and a top gate at least partially disposed on the plurality of gates such that the plurality of gates are at least partially disposed between the top gate and the quantum well stack.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a first gate above the quantum well stack, wherein the first gate includes a first gate metal; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal, and a material structure of the second gate metal is different from a material structure of the first gate metal; wherein the quantum well layer has a first strain under the first gate, a second strain under the second gate, and the first strain is different from the second strain.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.

Abstract: Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.

Abstract: Quantum computing assemblies with through-hole dies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a package substrate, a quantum processing die, and a through-hole die between the package substrate and the quantum processing die, wherein the quantum processing die is electrically coupled to the package substrate by interconnects extending through through-holes of the through-hole die.

Abstract: Disclosed herein are quantum dot device packages, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device package may include a die having a quantum dot device, wherein the quantum dot device includes a quantum well stack, gates disposed above the quantum well stack, and conductive pathways coupled between associated ones of the gates and conductive contacts of the die. The quantum dot device package may also include a package substrate, wherein conductive contacts are disposed on the package substrate, and first level interconnects are disposed between the die and the package substrate, coupling the conductive contacts of the die with associated conductive contacts of the package substrate.

Abstract: Embodiments of the present disclosure provide improved layout designs for quantum circuit assemblies employing qubits, e.g. superconducting qubits. One proposed design involves increasing a capacitance between a first qubit and a coupling component that couples the first qubit to a second qubit. Another design involves rounding of one or more corners at the end portions of coupling components. Yet another design involves varying the distance between two electrically conductive elements of a given superconducting qubit device which are connected to one another via one or more non-linear inductive elements. Qubit layout designs described herein may help increase coupling strength between qubits, allow greater design flexibility in achieving faster multi-qubit gates, and/or reduce or mitigate the negative effects of two-level systems.

Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. In one aspect of the present disclosure, a structure includes a first and a second interconnects provided over a surface of an interconnect support layer on which superconducting qubits are provided (which could be a substrate), a lower interconnect provided below such surface, and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. The lower interconnect includes a material of the interconnect support layer doped to be superconductive. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by doping the interconnect support layer, material for which could be selected, allows minimizing the amount of spurious TLS's in the areas surrounding below-plane interconnects.

Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. One structure includes a first and a second interconnects provided over a surface of an interconnect support layer, e.g. a substrate, on which superconducting qubits are provided, a lower interconnect provided below such surface (i.e. below-plane interconnect), and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by bonding of two substrates, material for which could be selected, allows minimizing the amount of spurious two-level systems in the areas surrounding below-plane interconnects while allowing different choices of materials to be used. Methods for fabricating such structures are disclosed as well.

Abstract: Disclosed herein are quantum dot devices with conductive liners, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base, a first fin extending from the base, a second fin extending from the base, a conductive material between the first fin and the second fin, and a dielectric material between the conductive material and the first fin.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.

Abstract: Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a gate disposed on a quantum well stack; an insulating material disposed on the gate; and a conductive via extending through the insulating material and in conductive contact with the gate.