Abstract: Systems and methods are provided for dynamically changing the operating clock frequency of a circuit. Control circuitry determines a first workload value for a circuit operating at a first clock frequency. Control circuitry then detect a second workload value for the circuit, which is less than the first workload value. When the control circuitry detects the second workload value, the control circuitry calculates a second clock frequency which is greater than the first clock frequency. The control circuitry then causes the circuit to operate at the second clock frequency.

Abstract: Mechanisms for reducing the impact of drive parameter writes on solid state drive (SSD) performance are provided, the methods including: saving one or more SSD drive parameters of an SSD to volatile memory of the SSD using an SSD controller; detecting a power-loss condition in the SSD; and copying the one or more SSD drive parameters from the volatile memory of the SSD to non-volatile memory of the SSD. In some embodiments, the SSD is a NAND SSD. In some embodiments, the one or more SSD drive parameters include one or more of: a drive health parameter, a drive internal statistic, drive thermal information, drive debug information, a number of host and non-volatile memory read and writes, media error handling data, temperature and throttle information, and firmware download information. In some embodiments, the volatile memory is one or more of: random-access memory and dynamic random-access memory.

Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Abstract: Read Quality of Service (rQoS) in the solid state drive is improved by reducing latency for host random read workloads. Host read operations for random read workloads are prioritized in the solid state drive over program operations for garbage collection to reduce latency for random read workloads. The program time (tProg) and other associated latencies such as program-suspend-resume overhead, and firmware process overhead to dispatch the program are minimized by minimizing the number of program commands used for garbage collection while the solid state drive is performing read operations for a random read workload for a host read operation, allowing the solid state drive to prioritize host read operations for random read workloads while ensuring that there is no impact to the amount of written data that is on the solid state drive.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, determine if a current workload for a particular NAND device of the plurality of NAND devices is a random write workload, and, if so determined, disable a program suspend operation for only the particular NAND device. Other embodiments are disclosed and claimed.

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

Abstract: A solid state drive (SSD) includes a nonvolatile memory array and a cache memory. The nonvolatile memory array has an encrypted integrated memory buffer (IMB) space. The cache memory has a decrypted copy of the IMB and an encrypted backup copy of the IMB. In power loss recovery (PLR) after a power loss imminent (PLI) event, the SSD can determine whether to recover the unencrypted copy of the IMB or the backup encrypted copy. The backup encrypted copy can reduce the risk of loss of data in the IMB in the event that multiple PLI events occur and a corrupted copy of the IMB is used to overwrite the IMB in the nonvolatile memory during a previous PLR.

Abstract: Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.

Abstract: An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.

Abstract: An embodiment of a semiconductor apparatus may include technology to detect a collision for a read request of an electronic storage device, and read data for the read request directly from a transfer buffer if the collision is detected. Other embodiments are disclosed and claimed.

Abstract: A refreshing method is described. The method includes recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of the data within the blocks, where, invalid data within the blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.

Abstract: An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform.

Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Abstract: A solid-state drive that can service multiple users or tenants and workloads (that is, multiple tenants) by enabling assigned bandwidth share of the solid-state drive across tenants is provided. The assigned bandwidth share is enabled for command submissions within a same assigned domain in addition to a weighted bandwidth share and quality of service control across different domains from all tenants.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory devices, and set a target order for the two or more memory devices based on the differentiator. Other embodiments are disclosed and claimed.

Abstract: A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

Abstract: Technology to dynamically modulate read granularity of a memory device. A computing system may include a controller and one or more memory devices coupled to the controller, the one or more memory devices including instructions, which when executed by the controller, may cause the computing system to determine whether a read to a memory device satisfies a sub-page read policy. In addition, the instructions, when executed, may cause the computing system to issue a sub-page read command to retrieve data from the memory device at sub-page granularity when the read satisfies the sub-page read policy. Moreover, the instructions, when executed, may cause the computing system to issue a full-page read command to retrieve the data at full-page granularity when the read does not satisfy the sub-page read policy or when a read for a segment of sequentially stored data does not satisfy the sub-page read policy.

Abstract: A solid state drive (SSD) includes a nonvolatile memory array and a cache memory. The nonvolatile memory array has an encrypted integrated memory buffer (IMB) space. The cache memory has a decrypted copy of the IMB and an encrypted backup copy of the IMB. In power loss recovery (PLR) after a power loss imminent (PLI) event, the SSD can determine whether to recover the unencrypted copy of the IMB or the backup encrypted copy. The backup encrypted copy can reduce the risk of loss of data in the IMB in the event that multiple PLI events occur and a corrupted copy of the IMB is used to overwrite the IMB in the nonvolatile memory during a previous PLR.