Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: A pipelined processor includes an instruction unit including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: There is provided a mechanism for propagating exception conditions in a computer system when instructions are subject to exception conditions. The apparatus includes a set of data registers for storing data manipulated by the instructions of the computer system, and a set of state registers for storing speculative states of data manipulated by the instructions, there being one state register associated with each data register. Furthermore, the apparatus includes a logic circuit, coupled to the set of state registers, for propagating the states from a source one of the state registers to a destination one of the state registers, if data stored in an associated source one of the data registers are used as a source for an associated destination one of data registers, and if data stored in the source data register were manipulated by a particular instruction subject to an exception condition.

Abstract: A compiler groups instructions into sets. The sets of instructions are related by data and control dependencies which are unresolvable by the compiler. Sets of instructions having unresolved dependencies are executed in a speculative state of the computer system under the assumption that an exception condition will not occur. However, if an exception condition does occur while executing a set of instructions in the speculative state, that exception condition is detected and the set of instructions is re-executed in a real state of the computer system to resolve the exception condition.

Abstract: An apparatus for enforcing that selected instructions are executed in a correct order, comprising a first content addressable memory for storing load addresses of data read from the memory by the selected instructions. The first content addressable memory comparing the store addresses with the load addresses of data to be written to the memory. The first content addressable memory generating a first signal, if one of the load addresses is identical to a subsequently compared one of the store addresses. The apparatus further including a second content addressable memory for storing and comparing states of the data read and written by the selected instructions. The second content addressable memory generating a second signal, if one of the stored states is identical to one of said compared states. The stored states including a program counter to repeat the execution of the selected instructions upon detecting the first and second signals.

Abstract: A method and device for receiving data in a synchronous communication system. Data can be accurately transferred between two subsystems in a synchronous system even where the clock skew and propagation delay between the two subsystems is unlimited. The receiving subsystem is initialized to ensure synchronous data transfer over a theoretically infinite range. The transmitting subsystem transmits data and a forwarded clock to the receiving subsystem. Data is captured in three state devices arranged in parallel to eliminate minimum delay requirements and to expand data valid time. The captured data is then aligned to the clock of the receiving subsystem by controlling a multiplexer which selects the proper state device output to pass to another state device for alignment to the receiving subsystem's clock. The multiplexer is controlled by a circuit which monitors the capturing of the incoming data and determines the correct state device output to select for proper data alignment.

Abstract: A next line prediction mechanism for predicting a next instruction index to an instruction cache of a computer pipeline, has a latency equal to the cycle time of the instruction cache to maximize the instruction bandwidth out of the instruction cache. The instruction cache outputs a block of instructions with each fetch initiated by a next instruction index provided by the line prediction mechanism. The instructions of the block are processed in parallel for instruction decode and branch prediction to maintain a high rate of instruction flow through the pipeline.

Abstract: A register map having a free list of available physical locations in a register file, a log containing a sequential listing of logical registers changed during a predetermined number of cycles, a back-up map associating the logical registers with corresponding physical homes at a back-up point in a computer pipeline operation and a predicted map associating the logical registers with corresponding physical homes at a current point in the computer pipeline operation. A set of valid bits is associated with the maps to indicate whether a particular logical register is to be taken from the back-up map or the predicted map indication of a corresponding physical home. The valid bits can be "flash cleared" in a single cycle to back-up the computer pipeline to the back-up point during a trap event.

Abstract: A method and arrangement for producing a predicted subroutine return address in response to entry of a subroutine return instruction in a computer pipeline that has a ring pointer counter and a ring buffer coupled to the ring pointer counter. The ring pointer counter contains a ring pointer that is changed when either a subroutine call instruction or return instruction enters the computer pipeline. The ring buffer has buffer locations which store a value present at its input into the buffer location pointed to by the ring pointer when a subroutine call instruction enters the pipeline. The ring buffer provides a value from the buffer location pointed to by the ring pointer when a subroutine return instruction enters the computer pipeline, this provided value being the predicted subroutine return address.

Abstract: The invention expands the period of data stabilization between state devices to be 1.5 times the cycle time minus the clock skew. The invention requires that a clock signal (hereinafter "forwarded clock") be sent with data to the receiving subsystem. Such data is received by a capture latch, which is operated by special logic that receives the forwarded clock, and then proceeds to an ordinary state device in the receiving subsystem that is running synchronously with the receiving subsystem. This state device nominally captures the data 1.5 cycles after it was sent from a state device in the sending subsystem.

Abstract: The invention is directed to a cache memory system in a data processor including a virtual cache memory, a physical cache memory, a virtual to physical translation buffer, a physical to virtual backmap, an Old-PA pointer and a lockout register. The backmap implements invalidates by clearing the valid flags in virtual cache memory. The Old-PA pointer indicates the backmap entry to be invalidated after a reference misses in the virtual cache. The physical address for data written to virtual cache memory is entered to Old-PA pointer by the translation buffer. The lockout register arrests all references to data which may have synonyms in virtual cache memory. The backmap is also used to invalidate any synonyms.

Abstract: Data can be accurately transmitted between two subsystems even if the clock skew between the two subsystems is larger than one clock cycle by the method of the invention. In one embodiment data is loaded into N state devices in the sending subsystem while the receiver recovers data from the sending state devices in rotation with an N input multiplexer. Another embodiment forwards a clock signal from the sending subsystem along with a data vector of N state signals for recovery by a pair of state devices capturing data on the rising and falling edges of the forwarded clock. A further embodiment achieves double bandwidth by forwarding two clock signals.

Abstract: The invention is directed to a method by which data from a first synchronous subsystem is transmitted to a second synchronous subsystem physically spaced from the first subsystem such that the system clock is skewed relative to the two subsystems. Pursuant to the invention, the transmitted data cycle time is multiple of the common system cycle time and a clock signal is forwarded with the data from the first subsystem to the second subsystem. The clock signal forwarded with the data provides an indication to the second subsystem of the instants of time at which received data changes. The data change instants are used to generate a binary signal that inverts its value at each such instant. The binary signal is transmitted through a synchronizer to produce a logic signal in the second subsystem. The logic signal is utilized to transmit the received data into the second subsystem in synchronization with the clock of the second subsystem.

Abstract: A cache memory system in a data processor that has a main memory and a processing unit, the cache memory system including a virtually addressed storage cache. This virtually addressed storage cache is connected to the main memory for storing in storage cache locations preselected portions of data from the main memory. Each cache location includes a valid indicator to indicate the data in the cache location is current. A translation buffers is coupled to the storage cache, and translates a virtual address to a physical address. The backmap is coupled to the storage cache and the translation buffer, and invalidates data in the storage cache by generating an invalidate index to the cache location at which a valid indicator is to be cleared only when data in the storage cache is to be invalidated. The cache memory system includes at least one lockout register for storing addresses for data which may exist in more than one storage location.

Abstract: Data can be accurately transmitted between two subsystems even if the clock skew between the two subsystems is larger than one clock cycle by the method of the invention. In one embodiment data is loaded into N state devices in the sending subsystem while the receiver recovers data from the sending state devices in rotation with an N input multiplexer. Another embodiment forwards a clock signal from the sending subsystem along with a data vector of N state signals for recovery by a pair of state devices capturing data on the rising and falling edges of the forwarded clock. A further embodiment achieves double bandwidth by forwarding two clock signals.