Abstract: A method of forming an edge termination structure in a semiconductor device is provided. The method includes: forming an epitaxial layer on a semiconductor substrate, the epitaxial layer extending laterally across active and edge termination regions in the device; forming active trenches in the active region and at least one outer trench in the edge termination region, each of the outer and active trenches extending vertically through at least a portion of the epitaxial layer; at least partially filling each of the outer and active trenches with a first insulating material; forming a moat by etching an area of the epitaxial layer in the edge termination region proximate to a last one of the plurality of active trenches in the active region; and at least partially filling the moat with a second insulating material to form a moat structure as an edge termination structure in the semiconductor device.

Abstract: An enhanced edge termination structure for use in a charge balanced semiconductor device is provided. The edge termination structure includes a plurality of edge termination trenches and a plurality of semiconductor mesa regions, each of the mesa regions being disposed between adjacent edge termination trenches. The edge termination trenches extend outwardly from an active region of the device on at least two adjacent sides of the active region when viewed in a plan view. The edge termination trenches are orthogonal to a corresponding edge of the active region from which they extend.

Abstract: A semiconductor device is provided that includes an epitaxial layer disposed on a semiconductor substrate, the epitaxial layer including an active region, in which at least one active element is formed, and an edge termination region, in which at least one edge termination structure is formed, the edge termination region being laterally adjacent to the active region. The semiconductor device further includes a charged layer disposed on an upper surface of the epitaxial layer, the charged layer covering at least a portion of the active region and extending laterally over at least a portion of the edge termination region. Active trenches may be formed in the active region, and at least one edge trench may be formed in the edge termination region. The charged layer may be formed on sidewalls of each of the active trenches and the edge trench using atomic layer deposition in a same processing step.

Abstract: A switching converter having a high-side switching transistor and a low-side switching transistor and an inductor, having a circuit for generating a simulated waveform representing a sawtooth inductor current waveform. A circuit for monitoring and voltage at a switch node between the high-side and low-side transistors to determine a time during which the inductor current is increasing and a time during which the inductor current is decreasing wherein voltage across the low-side transistor when it is conducting represents a first portion of the simulated sawtooth inductor current waveform. A circuit for utilizing the time when the inductor current is increasing, the time when the inductor current is decreasing and the voltage across the low-side transistor when it is conducting to generate a portion of the simulated inductor current waveform when the high-side transistor is conducting. A method and a power supply utilizing this circuit are also disclosed.

Abstract: A switching converter having a high-side switching transistor and a low-side switching transistor and an inductor, having a circuit for generating a simulated waveform representing a sawtooth inductor current waveform. A circuit for monitoring and voltage at a switch node between the high-side and low-side transistors to determine a time during which the inductor current is increasing and a time during which the inductor current is decreasing wherein voltage across the low-side transistor when it is conducting represents a first portion of the simulated sawtooth inductor current waveform. A circuit for utilizing the time when the inductor current is increasing, the time when the inductor current is decreasing and the voltage across the low-side transistor when it is conducting to generate a portion of the simulated inductor current waveform when the high-side transistor is conducting. A method and a power supply utilizing this circuit are also disclosed.

Abstract: A switching converter having a high-side switching transistor and a low-side switching transistor and an inductor, having a circuit for generating a simulated waveform representing a sawtooth inductor current waveform. A circuit for monitoring and voltage at a switch node between the high-side and low-side transistors to determine a time during which the inductor current is increasing and a time during which the inductor current is decreasing wherein voltage across the low-side transistor when it is conducting represents a first portion of the simulated sawtooth inductor current waveform. A circuit for utilizing the time when the inductor current is increasing, the time when the inductor current is decreasing and the voltage across the low-side transistor when it is conducting to generate a portion of the simulated inductor current waveform when the high-side transistor is conducting. A method and a power supply utilizing this circuit are also disclosed.

Abstract: A switching converter having a high-side switching transistor and a low-side switching transistor and an inductor, having a circuit for generating a simulated waveform representing a sawtooth inductor current waveform. A circuit for monitoring and voltage at a switch node between the high-side and low-side transistors to determine a time during which the inductor current is increasing and a time during which the inductor current is decreasing wherein voltage across the low-side transistor when it is conducting represents a first portion of the simulated sawtooth inductor current waveform. A circuit for utilizing the time when the inductor current is increasing, the time when the inductor current is decreasing and the voltage across the low-side transistor when it is conducting to generate a portion of the simulated inductor current waveform when the high-side transistor is conducting. A method and a power supply utilizing this circuit are also disclosed.

Abstract: A method for fabricating a power supply converter comprises a load inductor wrapped by a metal sleeve structured to transform the inductor into a heat sink positioned to deposit layers of solder paste on a sleeve surface and on the inductor leads. A metal carrier having a portion of a first thickness and portions of a greater second thickness is placed on the solder layers of the inductor. The carrier portion of first thickness is aligned with the inductor sleeve. The carrier portions of second thickness are aligned with the inductor leads. A sync and a control FET are placed side-by-side on solder layers deposited on the carrier portion of first thickness opposite the inductor sleeve. Reflowing is preformed and the solder layers are solidified. The FETs, the carrier and the inductor become integrated and the un-soldered surfaces of the FETs and the carrier portions of second thickness become coplanar.

Abstract: Systems and methods for regulating a switching converter are disclosed. One embodiment of the present invention relates to a power supply system that includes a switching converter that provides an output voltage by alternately turning on and off a high-side transistor and a low-side transistor both coupled to an output inductor through a switching node. The switching converter includes a drive circuit that regulates the output voltage based on a feedback signal. The power supply system also includes a simulated output generator that generates and provides the drive circuit with a simulated inductor waveform as the feedback signal based on a low-side output waveform of the low-side transistor measured at the switching node during off-times of the switching converter.

Abstract: A method for fabricating a power supply converter comprises a load inductor wrapped by a metal sleeve structured to transform the inductor into a heat sink positioned to deposit layers of solder paste on a sleeve surface and on the inductor leads. A metal carrier having a portion of a first thickness and portions of a greater second thickness is placed on the solder layers of the inductor. The carrier portion of first thickness is aligned with the inductor sleeve. The carrier portions of second thickness are aligned with the inductor leads. A sync and a control FET are placed side-by-side on solder layers deposited on the carrier portion of first thickness opposite the inductor sleeve. Reflowing is preformed and the solder layers are solidified. The FETs, the carrier and the inductor become integrated and the un-soldered surfaces of the FETs and the carrier portions of second thickness become coplanar.

Abstract: An apparatus includes a heat-generating component and a thermally inert component positioned in close proximity to the heat-generating component.

Abstract: A power supply converter (100) comprising a first FET (210) connected to ground (230), the first FET coupled to a second FET (220) tied to an input terminal (240), both FETs conductively attached side-by-side to a first surface of a metal carrier (120) and operating as a converter generating heat; and a packaged load inductor (110) tied to the carrier and an output terminal (241), the inductor package wrapped by a metal sleeve (113) in touch with the opposite surface of the metal carrier, the sleeve operable to spread and radiate the heat generated by the converter.

Abstract: A packaged power supply module (100) comprising a chip (110) with a first power field effect transistor (FET) and a second chip (120) with a second FET conductively attached side-by-side onto a conductive carrier (130), the transistors having bond pads of a first area (210) and the carrier having bond pads of a second area (230) smaller than the first area. Conductive bumps (114, 115, 124, 125) attached to the transistor bond pads and conductive bumps (126) attached to the carrier bond pads have equal volume and are coplanar (150), the bumps on the transistor pads having a first height and the bumps on the carrier pads having a second height greater than the first height.

Abstract: Systems and methods for regulating a switching converter are disclosed. One embodiment of the present invention relates to a power supply system that comprises a switching converter that provides an output voltage by alternately turning on and off a high-side transistor and a low-side transistor both coupled to an output inductor through a switching node. The switching converter includes a drive circuit that regulates the output voltage based on a feedback signal. The power supply system also comprises a simulated output generator that generates and provides the drive circuit with a simulated inductor waveform as the feedback signal based on a low-side output waveform of the low-side transistor measured at the switching node during off-times of the switching converter.

Abstract: A power supply module (400) comprising a metal leadframe with a pad (401) and a first metal clip (440) including a plate (440a), an extension (440b) and a ridge (440c); the plate and extension are spaced from the leadframe pad, and the ridge connected to an input supply. A synchronous Buck converter is in the space between the clip plate and the leadframe pad, the converter including a control FET die (410) soldered onto a sync FET die (420), the clip plate soldered to the control die having an input inductance (462), and the sync die soldered to the leadframe pad having an output capacitance. A capacitor (480a, 480b) integrated into the space between the clip extension and the leadframe pad, the clip extension soldered to the capacitor having a desired integrated inductance (463) operable to channel electrical energy from the switch node to ground.

Abstract: A packaged power supply module (100) comprising a chip (110) with a first power field effect transistor (FET) and a second chip (120) with a second FET conductively attached side-by-side onto a conductive carrier (130), the transistors having bond pads of a first area (210) and the carrier having bond pads of a second area (230) smaller than the first area. Conductive bumps (114, 115, 124, 125) attached to the transistor bond pads and conductive bumps (126) attached to the carrier bond pads have equal volume and are coplanar (150), the bumps on the transistor pads having a first height and the bumps on the carrier pads having a second height greater than the first height.

Abstract: A power supply converter (100) comprising a first FET (210) connected to ground (230), the first FET coupled to a second FET (220) tied to an input terminal (240), both FETs conductively attached side-by-side to a first surface of a metal carrier (120) and operating as a converter generating heat; and a packaged load inductor (110) tied to the carrier and an output terminal (241), the inductor package wrapped by a metal sleeve (113) in touch with the opposite surface of the metal carrier, the sleeve operable to spread and radiate the heat generated by the converter.

Abstract: A power supply module (400) comprising a metal leadframe with a pad (401) and a first metal clip (440) including a plate (440a), an extension (440b) and a ridge (440c); the plate and extension are spaced from the leadframe pad, and the ridge connected to an input supply. A synchronous Buck converter is in the space between the clip plate and the leadframe pad, the converter including a control FET die (410) soldered onto a sync FET die (420), the clip plate soldered to the control die having an input inductance (462), and the sync die soldered to the leadframe pad having an output capacitance. A capacitor (480a, 480b) integrated into the space between the clip extension and the leadframe pad, the clip extension soldered to the capacitor having a desired integrated inductance (463) operable to channel electrical energy from the switch node to ground.

Abstract: A high frequency power supply module (200) of a synchronous Buck converter stacking the control FET (210) and sync FET (220) and having the driver IC (230) integrated in the final package solution. A QFN leadframe has a rectangular flat pad (201) destined to become the heat spreader of the package; the leads (202) are positioned in line with two opposite sides of the pad, the other pad sides being free of leads. The sync FET die (220) is soldered to the pad; a first clip (240), soldered on the sync die, has the control die (210) attached by solder. A second clip (260) is soldered on top of the control die. Also soldered on the same pad, yet not stacked with the other dies, is IC driver chip (230). The IC driver is wire bonded (233) to the pins of the package and to the stacked dies. All die attach and clip attach use the same solder material in order to be reflowed in the same reflow step.

Abstract: A multi-chip module (MCM) provides power circuitry on a computer motherboard in a package of reduced size without sacrificing performance. The MCM co-packages essential power circuit components on a ball grid array (BGA) substrate. Two power MOSFETs disposed on the BGA substrate are connected in a half-bridge arrangement between an input voltage and ground. A MOSFET gate driver is electrically connected to respective gate inputs of the two power MOSFETs for alternately switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between the common output node and ground to minimize losses during deadtime conduction periods. The input capacitor of the circuit is contained within the MCM housing and is located close to the MOSFETs, reducing stray inductance in the circuit. The MCM package is thin and has dimensions of about 1 cm by 1 cm or less.