Patents by Inventor David Jauregui

David Jauregui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100171543
    Abstract: A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 8, 2010
    Applicant: Ciclon Semiconductor Device Corp.
    Inventors: Jacek Korec, Christopher F. Bull, Juan Alejandro Herbsommer, David Jauregui, Christopher B. Kocon
  • Patent number: 7242169
    Abstract: An apparatus and method for regulating a voltage to a load to compensate for one or more parasitic impedances. A first amplifier measures the voltage drop due to a first parasitic impedance, and a second amplifier measures the voltage drop due to a second parasitic impedance. An offset generator sums the first and second voltage drops with a reference voltage, and drives a DC-to-DC converter to produce an input voltage matching the summed voltages. Accordingly, the voltage at a load between the parasitic impedances matches the reference voltage. The load may be, for example, a computer microprocessor or central processing unit.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: July 10, 2007
    Assignee: Apple Inc.
    Inventors: Takashi Kanamori, Stephen J. Kim, David Jauregui
  • Publication number: 20060197509
    Abstract: An apparatus and method for regulating a voltage to a load to compensate for one or more parasitic impedances. A first amplifier measures the voltage drop due to a first parasitic impedance, and a second amplifier measures the voltage drop due to a second parasitic impedance. An offset generator sums the first and second voltage drops with a reference voltage, and drives a DC-to-DC converter to produce an input voltage matching the summed voltages. Accordingly, the voltage at a load between the parasitic impedances matches the reference voltage. The load may be, for example, a computer microprocessor or central processing unit.
    Type: Application
    Filed: March 1, 2005
    Publication date: September 7, 2006
    Inventors: Takashi Kanamori, Stephen Kim, David Jauregui
  • Patent number: 7098637
    Abstract: An improved active voltage positioning (AVP) implementation for a power supply for a microprocessor or the like includes an AVP circuit which is separated from the power supply error amplifier by a buffer amplifier having a parallel RC feedback circuit to controllably adjust the transient response. An AVP signal derived from an output load current sensing element provides an input to the buffer amplifier. A second input is provided by power supply reference voltage. A output of the buffer amplifier is connected as an input to the error amplifier to provide the AVP window. This permits separate adjustment of the transient behavior of the error loop and the AVP loop.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: August 29, 2006
    Assignee: International Rectifier Corporation
    Inventors: David Jauregui, Jason Zhang
  • Patent number: 6879491
    Abstract: A multi-chip module (MCM) provides power circuitry on a computer motherboard in a package of reduced size without sacrificing performance. The MCM co-packages essential power circuit components on a ball grid array (BGA) substrate. Two power MOSFETs disposed on the BGA substrate are connected in a half-bridge arrangement between an input voltage and ground. A MOSFET gate driver is electrically connected to respective gate inputs of the two power MOSFETs for alternately switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between the common output node and ground to minimize losses during deadtime conduction periods. The input capacitor of the circuit is contained within the MCM housing and is located close to the MOSFETs, reducing stray inductance in the circuit. The MCM package is thin and has dimensions of about 1 cm by 1 cm or less.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: April 12, 2005
    Assignee: International Rectifier Corporation
    Inventor: David Jauregui
  • Publication number: 20040240238
    Abstract: An improved active voltage positioning (AVP) implementation for a power supply for a microprocessor or the like includes an AVP circuit which is separated from the power supply error amplifier by a buffer amplifier having a parallel RC feedback circuit to controllably adjust the transient response. An AVP signal derived from an output load current sensing element provides an input to the buffer amplifier. A second input is provided by power supply reference voltage. A output of the buffer amplifier is connected as an input to the error amplifier to provide the AVP window. This permits separate adjustment of the transient behavior of the error loop and the AVP loop.
    Type: Application
    Filed: May 10, 2004
    Publication date: December 2, 2004
    Applicant: International Rectifier Corporation
    Inventors: David Jauregui, Jason Zhang
  • Publication number: 20030016505
    Abstract: A multi-chip module (MCM) provides power circuitry on a computer motherboard in a package of reduced size without sacrificing performance. The MCM co-packages essential power circuit components on a ball grid array (BGA) substrate. Two power MOSFETs disposed on the BGA substrate are connected in a half-bridge arrangement between an input voltage and ground. A MOSFET gate driver is electrically connected to respective gate inputs of the two power MOSFETs for alternately switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between the common output node and ground to minimize losses during deadtime conduction periods. The input capacitor of the circuit is contained within the MCM housing and is located close to the MOSFETs, reducing stray inductance in the circuit. The MCM package is thin and has dimensions of about 1 cm by 1 cm or less.
    Type: Application
    Filed: September 23, 2002
    Publication date: January 23, 2003
    Applicant: International Rectifier Corporation
    Inventor: David Jauregui
  • Publication number: 20020021560
    Abstract: A multi-chip module (MCM) provides power circuitry on a computer motherboard in a package of reduced size without sacrificing performance. The MCM co-packages essential power circuit components on a ball grid array (BGA) substrate. Two power MOSFETs disposed on the BGA substrate are connected in a half-bridge arrangement between an input voltage and ground. A MOSFET gate driver is electrically connected to respective gate inputs of the two power MOSFETs for alternately switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between the common output node and ground to minimize losses during deadtime conduction periods. The input capacitor of the circuit is contained within the MCM housing and is located close to the MOSFETs, reducing stray inductance in the circuit. The MCM package is thin and has dimensions of about 1 cm by 1 cm or less.
    Type: Application
    Filed: March 21, 2001
    Publication date: February 21, 2002
    Applicant: International Rectifier Corporation
    Inventor: David Jauregui