Patents by Inventor David Judd
David Judd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060194323Abstract: The present invention provides cell culture media formulations which support the in vitro cultivation of animal epithelial cells. The media comprise at least one fibroblast growth factor (FGF) and at least one agent that induces increased intracellular cAMP levels, and optionally comprise ascorbic acid. The present invention also provides methods of cultivating animal epithelial cells in vitro using these cell culture media formulations, kits comprising the media, cell culture compositions comprising the culture media and an animal epithelial cell, and compositions that may be used as replacements for organ or gland extracts in animal cell culture media.Type: ApplicationFiled: February 7, 2006Publication date: August 31, 2006Applicant: INVITROGEN CORPORATIONInventors: David Judd, Paul Battista
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Patent number: 7092401Abstract: An apparatus and method for managing reliable datagram work queues, and associated completion queues, using head and tail pointers with end-to-end context error cache are provided. Reliable datagram (RD) queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a RD queue page table index and a RD queue page index for identifying a position within the RD queue. For RD work queues, in the channel interface, the tail pointer is used to identify a next position where a work queue entry may be written and the head pointer is used only to determine whether the work queue is full. In the host channel adapter, the head pointer is used to identify a next work queue entry for processing and the tail pointer is used to determine if the queue is empty.Type: GrantFiled: November 15, 2001Date of Patent: August 15, 2006Assignee: International Business Machines CorporationInventors: David F. Craddock, Thomas Anthony Gregg, Ian David Judd, Gregory Francis Pfister, Renato John Recio
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Patent number: 6954882Abstract: A method and apparatus are provided for fault location in a loop network (100, 200, 400). The network system having a host port (214) for supplying and receiving data and a plurality of successively connected ports (201, 202, 203, 204, 205) through which data from the host port (214) is transferred. A counter (122) for each port records data transfers in which the amount of data received at a destination port is less than an expected amount of data. When a transfer with less than the expected amount of data is identified for a data flow between a sending port (201) and a destination port (214), the counters are incremented for each port (202, 203, 204, 205, 214) after the sending port up to and including the destination port. Analysing means determines a fault location in the network system from the distribution of counts in the counters (122).Type: GrantFiled: June 14, 2002Date of Patent: October 11, 2005Assignee: International Business Machines CorporationInventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Neil Morris, Robert Bruce Nicholson, Barry Douglas Whyte
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Patent number: 6789143Abstract: A distributed computing system having (host and I/O) end nodes, switches, routers, and links interconnecting these components is provided. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a message has been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism implements these queue pairs and completion queues in hardware. A mechanism for controlling the transfer of work requests from the consumer to the CA hardware and work completions from the CA hardware to the consumer using head and tail pointers that reference circular buffers is also provided. The QPs and CQs do not contain Work Queue Entries and Completion Queue Entries respectively, but instead contain references to these entries.Type: GrantFiled: September 24, 2001Date of Patent: September 7, 2004Assignee: International Business Machines CorporationInventors: David F. Craddock, Thomas Anthony Gregg, Ian David Judd, Gregory Francis Pfister, Renato John Recio, Donald William Schmidt
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Patent number: 6725296Abstract: An apparatus and method for managing work and completion queues using head and tail circular pointers. With the apparatus and method, queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a queue pointer table index and a queue page index for identifying a position within the queue. For work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty. For completion queues, the head pointer in the channel interface is used to identify a next completion queue entry to be processed.Type: GrantFiled: July 26, 2001Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: David F. Craddock, Thomas Anthony Gregg, Ian David Judd, Gregory Francis Pfister, Renato John Recio, Donald William Schmidt
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Publication number: 20030140277Abstract: A method and apparatus for relating a device name to a physical location of a device (202) on a network is provided. The network may be a serial loop network, for example a Fibre Channel Arbitrated Loop network. The network includes a plurality of devices (202) on or connected to the network (201) and a control device (205) with control over at least one of the devices (202). Each device (202) has a check output (204) independent of the network (201) with connection means (206) to a control device (205). The method includes the step of sending a device name from the check output (204) of a device (202) to the control device (205). The check output (204) of a device (202) is also connected to an external indication means for indicating the failure of the device (202).Type: ApplicationFiled: November 8, 2002Publication date: July 24, 2003Applicant: International Business Machines CorporationInventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Neil Morris, Robert Bruce Nicholson, Paul Jonathan Quelch, Barry Douglas White
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Publication number: 20030140099Abstract: A method and apparatus are provided for hard address conflict resolution for enclosures in a loop network (200). The loop network (200) has: a loop (202); a host means (201) on or connected to the loop (202); a plurality of devices (207) on or connected to the loop (202); and at least one enclosure containing one or more devices (207). Each device (207) has an address means. Each enclosure has an enclosure control device (208) with control over devices (207) in that enclosure. Each enclosure control device (208) has an address means. The method includes, at the start up of the loop network (200), setting the address means of the enclosure control devices (208) to a default value. Each device (207) is then entered in the loop (202) in a reset state in which only the enclosure control devices (208) and the host means (201) are active in the loop (202).Type: ApplicationFiled: November 8, 2002Publication date: July 24, 2003Applicant: International Business Machines CorporationInventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Neil Morris, Robert Bruce Nicholson, Paul Jonathan Quelch, Barry Douglas White
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Publication number: 20030091055Abstract: An apparatus and method for managing reliable datagram work queues, and associated completion queues, using head and tail pointers with end-to-end context error cache are provided. With the apparatus and method, reliable datagram (RD) queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a RD queue page table index and a RD queue page index for identifying a position within the RD queue. For RD work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty.Type: ApplicationFiled: November 15, 2001Publication date: May 15, 2003Applicant: International Business Machines CorporationInventors: David F. Craddock, Thomas Anthony Gregg, Ian David Judd, Gregory Francis Pfister, Renato John Recio
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Publication number: 20030058875Abstract: A distributed computing system is provided having (host and I/O) end nodes, switches, routers, and links interconnecting these components. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a message has been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism may implement these queue pairs and completion queues in hardware. A mechanism controls the transfer of work requests from the consumer to the channel adapter hardware using only head pointers in the hardware is described, along with a mechanism for passing work completions from the channel adapter hardware to the consumer using only tail pointers in the hardware. With this scheme the channel adapter hardware can inform the CI that a work request has been completed and provide the work completion information with just a single write to system memory.Type: ApplicationFiled: September 24, 2001Publication date: March 27, 2003Applicant: International Business Machines corporationInventors: Richard Louis Arndt, David F. Craddock, Thomas Anthony Gregg, Ian David Judd, Gregory Francis Pfister, Renato John Recio, Donald William Schmidt
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Publication number: 20030061296Abstract: A mechanism for initiating and completing one or more I/O transactions using memory semantic messages is disclosed. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than the simple transmission of a message.Type: ApplicationFiled: September 24, 2001Publication date: March 27, 2003Applicant: International Business Machines CorporationInventors: David F. Craddock, Charles Scott Graham, Ian David Judd, Renato John Recio, Timothy Jerry Schimke
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Publication number: 20030061417Abstract: A distributed computing system having (host and I/O) end nodes, switches, routers, and links interconnecting these components is provided. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a message has been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism implements these queue pairs and completion queues in hardware. A mechanism for controlling the transfer of work requests from the consumer to the CA hardware and work completions from the CA hardware to the consumer using head and tail pointers that reference circular buffers is also provided. The QPs and CQs do not contain Work Queue Entries and Completion Queue Entries respectively, but instead contain references to these entries.Type: ApplicationFiled: September 24, 2001Publication date: March 27, 2003Applicant: International Business Machines CorporationInventors: David F. Craddock, Thomas Anthony Gregg, Ian David Judd, Gregory Francis Pfister, Renato John Recio, Donald William Schmidt
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Publication number: 20030056153Abstract: A method and apparatus are provided for fault location in a loop network (100, 200, 400). The network system having a host port (214) for supplying and receiving data and a plurality of successively connected ports (201, 202, 203, 204, 205) through which data from the host port (214) is transferred. A counter (122) for each port records data transfers in which the amount of data received at a destination port is less than an expected amount of data; When a transfer with less than the expected amount of data is identified for a data flow between a sending port (201) and a destination port (214), the counters are incremented for each port (202, 203, 204, 205, 214) after the sending port up to and including the destination port. Analysing means determines a fault location in the network system from the distribution of counts in the counters (122).Type: ApplicationFiled: June 14, 2002Publication date: March 20, 2003Applicant: International Business Machines CorporationInventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Neil Morris, Robert Bruce Nicholson, Barry Douglas Whyte
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Publication number: 20030050990Abstract: A mechanism for initiating and completing one or more I/O transactions using memory semantic messages in a system area network is disclosed. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than a simple “channel semantic” transmission of a message. The use of memory semantic input/output in this way facilitates the migration of input/output adapters from a memory-mapped interface, such as Peripheral Component Interconnect (PCI), to a system area network.Type: ApplicationFiled: June 21, 2001Publication date: March 13, 2003Applicant: International Business Machines CorporationInventors: David F. Craddock, Charles Scott Graham, Ian David Judd, Renato John Recio
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Publication number: 20030046474Abstract: A mechanism for initiating and completing one or more I/O transactions using channel and memory semantic messages is disclosed. Channel semantic messages are messages that are simply packetized and transmitted. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than the simple transmission of a message.Type: ApplicationFiled: June 21, 2001Publication date: March 6, 2003Applicant: International Business Machines CorporationInventors: David F. Craddock, Charles Scott Graham, Ian David Judd, Renato John Recio
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Publication number: 20030023786Abstract: An apparatus and method for managing work and completion queues using head and tail circular pointers. With the apparatus and method, queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a queue pointer table index and a queue page index for identifying a position within the queue. For work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty. For completion queues, the head pointer in the channel interface is used to identify a next completion queue entry to be processed.Type: ApplicationFiled: July 26, 2001Publication date: January 30, 2003Applicant: International Business Machines CorporationInventors: David F. Craddock, Thomas Anthony Gregg, Ian David Judd, Gregory Francis Pfister, Renato John Recio, Donald William Schmidt
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Publication number: 20030018828Abstract: A method and system for transmitting and receiving data from a host computer system to an Ethernet adapter are provided. The method comprises establishing a connection between the host system and the Ethernet adapter pushing a transmit or receive request message from a host system device driver to the Ethernet adapter's request queue. Access to host memory is transferred to the Ethernet adapter. If data is being transmitted to the Ethernet adapter, the adapter reads the data from a location in host memory specified in the transmit request message, and then transmits the data onto transmission media (e.g. wire, fiber). If the request message is a receive request, the adapter reads the data from the media and then sends the data into host memory at the location specified in the receive request message. When the data transfer is complete, the adapter sends a response message back to the host.Type: ApplicationFiled: June 29, 2001Publication date: January 23, 2003Applicant: International Business Machines CorporationInventors: David F. Craddock, Ian David Judd, Renato John Recio, Lee Anton Sendelbach
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Publication number: 20030005352Abstract: A method and apparatus for recovery from faults in a loop network (400) is provided. The loop network (400) has a host means (402), a first loop and a second loop (406, 408), a plurality of ports (410) connected to each of the loops (406, 408) and a control device (414, 440) on or connected to each loop (406, 408) with bypass control over at least one of the ports (410) connected to the loop (406, 408). In the event of a failure on the first loop (406), the host means (402) instructs the bypassing of at least one port (410) on the first loop (406), the host means (402) sending the instructions via the control device (414, 440) on or connected to the second loop (408).Type: ApplicationFiled: May 17, 2002Publication date: January 2, 2003Applicant: International Business Machines CorporationInventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Neil Morris, Robert Bruce Nicholson, Barry Douglas Whyte
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Publication number: 20030005368Abstract: A method and apparatus for recovery from faults in a loop network (500) is provided. The loop network (500) has a plurality of ports (520, 530, 532, 534) serially connected with means for bypassing the ports (520, 530, 532, 534) from the loop network (500). A control device (522, 524) is provided with bypass control over at least one of the ports (530, 532, 534). A host means (502) sends a command to the control device (522, 524) at regular intervals and the control device (522, 524) has a counter which restarts a time period at the receipt of each command. If the time period expires, the control device (522, 524) activates the means for bypassing all the ports (530, 532, 534) under its control. The loop network (500) may have two loops (516, 518) with at least some of the ports (520, 530, 532, 534) common to both loops (516, 518).Type: ApplicationFiled: May 17, 2002Publication date: January 2, 2003Applicant: International Business Machines CorporationInventors: Reginald Beer, Paul Nicholas Cashman, Paul Hooton, Ian David Judd, Robert Frank Maddock, Robert Bruce Nicholson, Barry Douglas Whyte
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Publication number: 20020198927Abstract: An apparatus and method for an advanced tunneling technique to allow Internet Protocol (IP) frames to be routed through System Area Network (SAN) components with little or no overhead are provided. Furthermore, an apparatus and method for processing Internet Protocol (IP) version 6 datagrams over a SAN using basic raw and unreliable datagram (RawD and UD respectively) interfaces are provided. The apparatus and method allows a host channel adapter (HCA) to attach directly to an IP router which supports multiple link protocols, for example a router than attaches InfiniBand (IB) links and Ethernet links, and uses IP as the networking protocol on both. In this way, a SAN may be coupled to a LAN via a router with minimal hardware and overhead.Type: ApplicationFiled: June 21, 2001Publication date: December 26, 2002Applicant: International Business Machines CorporationInventors: David F. Craddock, Charles Scott Graham, Ian David Judd, Vivek Kashyap, Renato John Recio, Lee Anton Sendelbach
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Patent number: 6467022Abstract: A Solid State Disk (“SSD”) and accompanying logic to extend the local memory of an adapter for RAID storage devices. Use of virtual memory, representing the SSD range of addresses in the adapter address memory, allows the adapter to incorporate the total memory into the adapter memory structure. The SSD is non-volatile and large amounts of cache items may be transferred to the SSD as an extension of the adapter memory. The cache write may be delayed and subsequently written to a designated address on a RAID drive, freeing the adapter on-board memory and control functions. Further, the size of the SSD allows for large amounts of data staging and storage, permitting device-to-device communications that would reduce the read and write commands between the host, adapter and drives.Type: GrantFiled: November 3, 2000Date of Patent: October 15, 2002Assignee: International Business Machines CorporationInventors: Pat Allen Buckland, Ian David Judd, Gary Robert Lyons, Renato John Recio, Michael Francis Scully