Patents by Inventor David Judd

David Judd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6467001
    Abstract: The present invention provides a method and a system for connecting together, in a VLSI chip, a plurality of macros which require data flow connections between each other. A simple standard interface is realised between all macros. Any number of macros can be connected together, also allowing concurrent transactions between 4 or more macros using a cross-bar switch. Each macro may be a master (capable of requesting connections), a slave (capable of receiving connections from a master) or both. The centralised inter-connect logic includes three major components: the cross-bar switch, which makes the connections between the macros, the address decoder, which determines which slave each master wishes to connect to and an arbiter, which arbitrates between the macros when two or more masters request a connection simultaneously.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: October 15, 2002
    Assignee: International Business Machines Corporation
    Inventors: Mandy Alexander Gray, Michael J. Palmer, Ian David Judd
  • Patent number: 6128674
    Abstract: The system I/O interface and its data structure are designed to minimize the host CPU utilization in driving an adapter. The interface is also designed to reduce the system interference in processing I/O requests. To eliminate the need of using PIO instructions, the command/status blocks for exchanging messages between the system and the adapter reside in the system memory. The data structure is designed to avoid "share write" entries in order to further minimize the overhead of maintaining each coherency when updating an entry in the cache either concurrently or sequentially by both adapter and system CPU. Further, the data structure of the control and status blocks is resided in the system memory. The system CPU uses STORE instruction to prepare control blocks and LOAD instruction to read from completion status blocks; while the adapter will rely on its DMA engine to move data to/from system memory in accessing control/status blocks.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: October 3, 2000
    Assignee: International Business Machines Corporation
    Inventors: Bruce Leroy Beukema, Patrick Allen Buckland, Wen-Tzer Thomas Chen, David Arlen Elko, Ian David Judd, Renato John Recio
  • Patent number: 6118612
    Abstract: A spindle synchronization technique is described which is useful in a disk array subsystem comprising a plurality of disk drives (40,41,42,43) connected by means of serial links (25,26,27,28) to a disk drive controller (20). Data and command information is transmitted over the link in the form of multi-character frames, the flow of which is regulated by special ten bit protocol characters. A SYNC protocol character is defined which is used to synchronize the spindles of the disk drives. This SYNC character is issued by controller to selected ones of the drives over the same link used for the transmission of the command and data information. The SYNC character may be interleaved between the characters of frames being transmitted over the link.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: September 12, 2000
    Assignee: International Business Machines Corporation
    Inventors: Ian David Judd, Norman Apperley
  • Patent number: 6038618
    Abstract: A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit on each of the first and second communication links between each of the first and second ports and the first and second data storage devices, the bypassing means being operable to bypass the host computer by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: March 14, 2000
    Assignee: International Business Machines Corporation
    Inventors: Reginald Beer, Peter John Deacon, Ian David Judd, Neil Morris
  • Patent number: 5958064
    Abstract: An error recovery method for use in an information communication system which comprises a plurality of nodes connected by links. Information is transferred between the nodes in frames of predefined types, including at least a first frame type used to transfer data and a second frame type used for error recovery. Each node has at least a first and a second mode of operation. In the first mode frames of both first and second types are accepted. In the second mode frames of the first type are discarded and only frames of the second type are accepted. A master node which controls error recovery is selected from amongst those nodes which can initiate transfers.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: September 28, 1999
    Assignee: International Business Machines Corporation
    Inventors: Ian David Judd, Reginald Beer
  • Patent number: 5933435
    Abstract: Described is a system and method of communicating between first and second nodes connected by a serial link wherein the data is transmitted between the nodes in the form of packets made up of multiple bit frames. Each packet that is correctly received by the second node is acknowledged by means of a pair of multibit frames. These frames may be interleaved among the frames making up any outgoing data packet that is being transmitted by the second node. The technique employed provides unambiguous acknowledgment of each data packet and if a data packet is received incorrectly, the packet is available in a buffer in the first node for resending.
    Type: Grant
    Filed: September 25, 1992
    Date of Patent: August 3, 1999
    Assignee: International Business Machines Corporation
    Inventors: Vinay Velji Shah, Ian David Judd, Reginald Beer
  • Patent number: 5893138
    Abstract: Disclosed is an array controller for controlling the transfer of data from a host system to an array of data storage devices, comprising a processor connected via a local bus to a data buffer in which data is staged during said transfer. The array controller is provided with a buffer controller for controlling the operation of the buffer and is further provided with channel hardware for manifesting a plurality of data channels, selectable by the local bus address, over which data is transferred in and out of the data buffer.
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: April 6, 1999
    Assignee: International Business Machines Corporation
    Inventors: Ian David Judd, Stephen G. Luning
  • Patent number: 5768623
    Abstract: A system is provided for storing data for a plurality of host computers on a plurality of storage arrays so that data on each storage array can be accessed by any host computer. A plurality of adapter cards are used. Each adapter has controller functions for a designated storage array. There is an adapter communication interface (interconnect) between all of the adapters in the system. There is also a host application interface between an application program running in the host computer and an adapter. When a data request is made by an application program to a first adapter through a host application interface for data that is stored in a storage array not primarily controlled by the first adapter, the data request is communicated through the adapter communication interface to the adapter primarily controlling the storage array in which the requested data is stored.
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: June 16, 1998
    Assignee: International Business Machines Corporation
    Inventors: Ian David Judd, Nik Shaylor, Alistair Leask Symon