Patents by Inventor David K. Hwang
David K. Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8178911Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: GrantFiled: September 8, 2011Date of Patent: May 15, 2012Assignee: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm
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Publication number: 20120003810Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: ApplicationFiled: September 8, 2011Publication date: January 5, 2012Applicant: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm
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Publication number: 20110318921Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.Type: ApplicationFiled: September 7, 2011Publication date: December 29, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
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Patent number: 8030168Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.Type: GrantFiled: April 6, 2009Date of Patent: October 4, 2011Assignee: Micron Technology, Inc.Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
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Patent number: 8022473Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: GrantFiled: February 16, 2011Date of Patent: September 20, 2011Assignee: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm
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Publication number: 20110133263Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: ApplicationFiled: February 16, 2011Publication date: June 9, 2011Applicant: Micron Technology, Inc.Inventors: DAVID K. HWANG, Larson Lindholm
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Patent number: 7948030Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: GrantFiled: September 3, 2010Date of Patent: May 24, 2011Assignee: Micron Technology, Inc.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Patent number: 7935999Abstract: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.Type: GrantFiled: February 22, 2010Date of Patent: May 3, 2011Assignee: Micron Technology, Inc.Inventors: Gordon A. Haller, David K. Hwang, Sanh Dang Tang, Ceredig Roberts
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Patent number: 7897465Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: GrantFiled: March 15, 2010Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm
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Publication number: 20100327369Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: ApplicationFiled: September 3, 2010Publication date: December 30, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Patent number: 7808041Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: GrantFiled: December 1, 2009Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Publication number: 20100171170Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: ApplicationFiled: March 15, 2010Publication date: July 8, 2010Applicant: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm
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Publication number: 20100148249Abstract: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.Type: ApplicationFiled: February 22, 2010Publication date: June 17, 2010Applicant: Micron Technology, Inc.Inventors: Gordon A. Haller, David K. Hwang, Sanh Dang Tang, Ceredig Roberts
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Patent number: 7696568Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: GrantFiled: May 21, 2007Date of Patent: April 13, 2010Assignee: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm
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Patent number: 7687342Abstract: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.Type: GrantFiled: September 1, 2005Date of Patent: March 30, 2010Assignee: Micron Technology, Inc.Inventors: Gordon A. Haller, David K. Hwang, Sanh Dang Tang, Ceredig Roberts
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Publication number: 20100072557Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: ApplicationFiled: December 1, 2009Publication date: March 25, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Patent number: 7648915Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: GrantFiled: January 12, 2007Date of Patent: January 19, 2010Assignee: Micron Technology, Inc.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Patent number: 7601591Abstract: The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material.Type: GrantFiled: January 28, 2008Date of Patent: October 13, 2009Assignee: Micron Technology, Inc.Inventors: David K. Hwang, Kunal Parekh, Michael Willett, Jigish Trivedi, Suraj Mathew, Greg Peterson
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Publication number: 20090197386Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.Type: ApplicationFiled: April 6, 2009Publication date: August 6, 2009Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
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Patent number: 7563723Abstract: Methods of etching substrates with small critical dimensions and altering the critical dimensions are disclosed. In one embodiment, a sulfur oxide based plasma is used to etch an amorphous carbon hard mask layer. The features of a pattern can be shrunk using a plasma etch to reduce the resist elements on the surface of the masking structure. Features in the pattern can also be enlarged by depositing polymer on the resist elements or by sloping an underlying layer. In one preferred embodiment, features of the pattern are shrunk before being enlarged in order to reduce line edge roughness.Type: GrantFiled: August 3, 2006Date of Patent: July 21, 2009Assignee: Micron Technology, Inc.Inventors: Mirzafer K. Abatchev, David K. Hwang, Robert G. Veltrop