Abstract: A processor, a method and a computer-readable storage medium for encrypting a return address are provided. The processor comprises hardware logic configured to encrypt an instruction pointer and push the encrypted instruction pointer onto a stack. The logic is further configured to retrieve the encrypted instruction pointer from the stack, decrypt the instruction pointer and redirect execution to the decrypted instruction pointer.

Abstract: The present invention relates to compositions and methods for diagnosing and treating diseases, disorders or conditions associated with dysregulated expression of GPC3. The invention provides novel antibodies that specifically bind to glypican-3 (GPC3). The invention also relates to a fully human chimeric antigen receptor (CAR) wherein the CAR is able to target GPC3.

Abstract: A single or multicore processor having a separate hardware cryptographic engine (HCE) for microcode patch updates is presented. Microcode in each core is modified to utilize the HCE for patch updates. Various arrangements are presented. Memory for HCE processing can include shared L2 or L3 memory or a separate DRAM configured in the address space of each core or set of cores and the HCE. In some embodiments, the HCE may be located on a circuit card attached to an extension bus, such as a PCIe or LPC bus.

Abstract: We have discovered that p63 inhibition results in increased cellular proliferation. We have also performed a screen for agents capable of increasing cellular proliferation, (e.g., of stem cells such as skin-derived precursors (SKPs)). The invention therefore invention provides compositions, methods, and kits for increasing proliferation of cells, using compounds that decrease p63 expression or activity or using the compounds described herein. The invention also features methods of using these compounds for increasing hair growth, improving skin health, or promoting skin repair in a subject.

Abstract: The present invention provides a method and apparatus for use with a hierarchical cache system. The method may include concurrently flushing one or more first caches and a second cache of a multi-level cache. Each first cache is smaller and at a lower level in the multi-level cache than the second level cache.

Abstract: Methods of treating individuals with a glucose metabolism disorder, and compositions thereof, are provided.

Abstract: The invention relates to methods and compositions for preparing silk-based piezoelectric materials and methods for increasing piezoelectricity in silk matrices.

Abstract: According to an aspect of the presently disclosed subject matter there is provided a method of interactive communication, comprising: receiving a first usage data communication including user data, a first usage progression data and a product data; processing the first usage data to determine a corresponding first usage state based at least on the first usage progression data and at least one of the user data or the product data; selecting a first action based on the first usage state; providing a first interactive communication to a user that is associated with the first usage data, the first interactive communication can be configured to enable the user to execute the selected first action.

Abstract: A method and apparatus for picking load or store instructions is presented. Some embodiments of the method include determining that the entry in the queue includes an instruction that is ready to be executed by the processor based on at least one instruction-based event and concurrently determining cancel conditions based on global events of the processor. Some embodiments also include selecting the instruction for execution when the cancel conditions are not satisfied.

Abstract: A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided.

Abstract: A method includes performing a speculative tablewalk. The method includes performing a tablewalk to determine an address translation for a speculative operation and determining whether the speculative operation has been upgraded to a non-speculative operation concurrently with performing the tablewalk. An apparatus is provided that includes a load-store unit to maintain execution operations. The load-store unit includes a tablewalker to perform a tablewalk and includes an input indicative of the operation being speculative or non-speculative as well as a state machine to determine actions performed during the tablewalk based on the input. The apparatus also includes a translation look-aside buffer. Computer readable storage devices for performing the methods and adapting a fabrication facility to manufacture the apparatus are provided.

Abstract: A method of operating a processor includes reclaiming a physical register renamed as a microcode architectural register used by a microcode routine. The physical register is reclaimed according to an indicator corresponding to the microcode architectural register and indicating that a pointer to the physical register and corresponding to the microcode architectural register is an active pointer.

Abstract: In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt.

Abstract: Compositions and methods for modulating levels of PLA2G12A are provided. Methods for treating various conditions, such as conditions that are associated with or that result in reduced muscle function and/or muscle mass, are provided. Methods for modulating glucose and/or insulin levels in glucose metabolism disorders are provided.

Abstract: A method is provided for dispatching a load operation to a processing device and determining that the operation is the oldest load operation. The method also includes executing the operation in response to determining the operation is the oldest load operation. Computer readable storage media for performing the method are also provided. An apparatus is provided that includes a translation look-aside buffer (TLB) content addressable memory (CAM), and includes an oldest operation storage buffer operationally coupled to the TLB CAM. The apparatus also includes an output multiplexor operationally coupled to the TLB CAM and to the oldest operation storage buffer. Computer readable storage media for adapting a fabrication facility to manufacture the apparatus are also provided.

Abstract: The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with a plurality of load or store operations.

Abstract: Methods of treating individuals with a glucose metabolism disorder, and compositions thereof, are provided.

Abstract: The present disclosure relates to biophotonic sensors. An example of a biophotonic sensor may be an apparatus for analyzing a sample. The apparatus may include a substrate, aperiodic nanostructured protrusions disposed on the substrate, and a silk material deposited between the protrusions.

Abstract: A method of manufacturing a biopolymer optical device includes providing a polymer, providing a substrate, casting the polymer on the substrate, and enzymatically polymerizing an organic compound to generate a conducting polymer between the provided polymer and the substrate. The polymer may be a biopolymer such as silk and may be modified using organic compounds such as tyrosines to provide a molecular-level interface between the provided bulk biopolymer of the biopolymer optical device and a substrate or other conducting layer via a tyrosine-enzyme polymerization. The enzymatically polymerizing may include catalyzing the organic compound with peroxidase enzyme reactions. The result is a carbon-carbon conjugated backbone that provides polymeric “wires” for use in polymer and biopolymer optical devices. An all organic biopolymer electroactive material is thereby provided that provides optical functions and features.

Abstract: In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt.