Abstract: The invention provides a subassembly to facilitate co-planar vertical surface mounting of subassembly boards. By “vertically mounting” is meant that a subassembly circuit board with a major surface is mounted perpendicular to the major surface of a circuit motherboard. In accordance with the invention, a subassembly for co-planar vertical surface mounting comprises a subassembly board coupled between a pair of base headers. Advantageously one base header comprises a plurality of mounting lugs secured to a transverse element in a co-planar configuration. The other base header conveniently comprises a plurality of connector pins secured to an elongated header element in co-planar configuration. The two headers interlock with the board to provide connection and co-planar support. A pickup cap attached at the board edge opposite the base permits pick-and-place positioning of the subassembly by conventional equipment without the need for special grippers.

Abstract: A semiconductor chip package that includes a DC-DC converter implemented with a land grid array (LGA) package for interconnection and surface mounting to a printed circuit board. The LGA package integrates all required active components of the DC-DC power converter, including a synchronous buck PWM controller, driver circuits, and MOSFET devices. In particular, the LGA package comprises a substrate having a top surface and a bottom surface, with a DC-DC converter provided on the substrate. The DC-DC converter including at least one power silicon die disposed on the top surface of the substrate. A plurality of electrically and thermally conductive pads are provided on the bottom surface of the substrate in electrical communication with the DC-DC converter through respective conductive vias. The plurality of pads include first pads having a first surface area and second pads having a second surface area, the second surface area being substantially larger than the first surface area.

Abstract: A semiconductor chip package that includes a DC-DC converter implemented with a land grid array for interconnection and surface mounting to a printed circuit board. The package includes a two layer substrate comprising a top surface and a bottom surface. At least one via array extends through the substrate. Each via in a via array includes a first end that is proximate to the top surface of the substrate and a second end that is proximate to the bottom surface of the substrate. At least one die attach pad is mounted on the top surface of the substrate and is electrically and thermally coupled to the via array. The DC-DC converter includes at least one power semiconductor die having a bottom surface that forms an electrode. The power semiconductor die is mounted on a die attach pad such that the bottom surface of the die is in electrical contact with the die attach pad. The bottom of the package forms a land grid array.

Abstract: A carrier board which has a plurality of conduction layers is provided. A plurality of electronic units are produced on surface regions of the board with electronic components arranged at regular spacing. The surface regions, for use in a separation operation, are held at predetermined separating regions to a frame. The frame has an externally contactable, connecting region for an operating voltage or load for electronic units. Each electronic unit can be acted upon with the operating voltage or a load, by way of supply, load and/or signal lines in the frame and at separating regions of the carrier board. The electronic units can be operated and tested by the supply as well as the load and/or signal lines in a full-load mode of operation.

Abstract: The invention concerns an apparatus for producing and testing a plurality of preferably identical electronic units. A carrier board member which includes a circuit board material and which has a plurality of conduction layers is provided. A plurality of electronic units can be produced on surface regions of the carrier board member by an automated fitting process with electronic components arranged at regular spacings from each other. The surface regions are held at predetermined separating regions of the carrier board member, which are designed for a separation operation, to a frame region which extends around the surface regions. The carrier board member in the frame region has an externally contactable, central, electrical connecting region for an operating voltage or load for the plurality of electronic units.

Abstract: A method is disclosed which enhances the ability of digital computer system to manage displays, especially in an environment where a single physical display supports a plurality of logical displays (windows). Machine-language instructions are provided which, in conjunction with user-supplied form descriptors describing each of the windows, enable management and generation of display image data to be performed directly by the processing hardware of the digital computer system, eliminating any need for intervening interpretive software. Data computed from form descriptors may be encached, enhancing the speed of consecutive operations on windows. Graceful creation is enhanced by permitting processing control to escape to software fault handlers.