Abstract: Semiconductor devices and systems with self-aligned backside contacts, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a channel, a source and a drain, source and drain contacts, and a gate. The channel includes multiple channel structures arranged vertically and substantially in parallel. The source and the drain are at opposite ends of the channel. The source and drain contacts are coupled to the source and the drain, respectively. Moreover, one of the source contact or the drain contact is above the source or the drain and the other of the source contact or the drain contact is below the source or the drain. The gate is around the channel structures, where a portion of the gate below the channel structures is thicker than respective portions of the gate between the channel structures in cross-section view.

Abstract: A dopant may included in one or more sacrificial layers, e.g., silicon layers or silicon germanium layers, used for forming nanoribbon transistors. Adding a dopant to a silicon germanium layer may cause the silicon germanium to be more stress neutral, to prevent relaxation after etching stacks of individuated nanoribbons. Alternatively, when added to one or more sacrificial layers of silicon, the doped silicon layers may counteract elastic stress from the silicon germanium layers. The dopant layers may be included at various positions in a stack of materials. The dopant layer may include one or more dopants selected from carbon, arsenic, boron, and phosphorus.

Abstract: Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon.

Abstract: A method for forming a forming a semiconductor structure is disclosed. The method may include: forming a silicon oxide layer on a surface of a substrate, depositing a silicon germanium (Si1-xGex) seed layer directly on the silicon oxide layer, and depositing a germanium (Ge) layer directly on the silicon germanium (Si1-xGex) seed layer. Semiconductor structures including a germanium (Ge) layer deposited on silicon oxide utilizing an intermediate silicon germanium (Si1-xGex) seed layer are also disclosed.

Abstract: Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon.

Abstract: In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.

Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.

Abstract: A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

Abstract: A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

Abstract: A photodetector structure over a partial length of a silicon waveguide structure within a photonic integrated circuit (PIC) chip. The photodetector structure is embedded within a cladding material surrounding the waveguide structure. The photodetector structure includes an absorption region, for example comprising Ge. A sidewall of the cladding material may be lined with a sacrificial spacer. After forming the absorption region, the sacrificial spacer may be removed and passivation material formed over a sidewall of the absorption region. Between the absorption region an impurity-doped portion of the waveguide structure there may be a carrier multiplication region, for example comprising crystalline silicon. If present, edge facets of the carrier multiplication region may be protected by a spacer material during the formation of an impurity-doped charge carrier layer. Occurrence of edge facets may be mitigated by embedding a portion of the photodetector structure with a thickness of the waveguide structure.

Abstract: An apparatus and a method for forming a 3-D NAND device are disclosed. The method of forming the 3-D NAND device may include forming a plug fill and a void. Advantages gained by the apparatus and method may include a lower cost, a higher throughput, little to no contamination of the device, little to no damage during etching steps, and structural integrity to ensure formation of a proper stack of oxide-nitride bilayers.

Abstract: Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon.

Abstract: A method for depositing a boron doped silicon germanium (Si1-xGex) film is disclosed. The method may include: providing a substrate within a reaction chamber; heating the substrate to a deposition temperature; flowing a silicon precursor, a germanium precursor, and a halide gas into the reaction chamber through a first gas injector; flowing a boron dopant precursor into the reaction chamber through a second gas injector independent from the first gas injector; contacting the substrate with the silicon precursor, the germanium precursor, the halide gas and the boron dopant precursor; and depositing the boron doped silicon germanium (Si1-xGex) film over a surface of the substrate.

Abstract: A method for forming a forming a semiconductor structure is disclosed. The method may include: forming a silicon oxide layer on a surface of a substrate, depositing a silicon germanium (Si1?xGex) seed layer directly on the silicon oxide layer, and depositing a germanium (Ge) layer directly on the silicon germanium (Si1?xGex) seed layer. Semiconductor structures including a germanium (Ge) layer deposited on silicon oxide utilizing an intermediate silicon germanium (Si1?xGex) seed layer are also disclosed.

Abstract: A method for forming a forming a semiconductor structure is disclosed. The method may include: forming a silicon oxide layer on a surface of a substrate, depositing a silicon germanium (Si1-xGex) seed layer directly on the silicon oxide layer, and depositing a germanium (Ge) layer directly on the silicon germanium (Si1-xGex) seed layer. Semiconductor structures including a germanium (Ge) layer deposited on silicon oxide utilizing an intermediate silicon germanium (Si1-xGex) seed layer are also disclosed.

Abstract: A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

Abstract: An apparatus and a method for forming a 3-D NAND device are disclosed. The method of forming the 3-D NAND device may include forming a plug fill and a void. Advantages gained by the apparatus and method may include a lower cost, a higher throughput, little to no contamination of the device, little to no damage during etching steps, and structural integrity to ensure formation of a proper stack of oxide-nitride bilayers.

Abstract: A method for depositing a boron doped silicon germanium (Si1-xGex) film is disclosed. The method may include: providing a substrate within a reaction chamber; heating the substrate to a deposition temperature; flowing a silicon precursor, a germanium precursor, and a halide gas into the reaction chamber through a first gas injector; flowing a boron dopant precursor into the reaction chamber through a second gas injector independent from the first gas injector; contacting the substrate with the silicon precursor, the germanium precursor, the halide gas and the boron dopant precursor; and depositing the boron doped silicon germanium (Si1-xGex) film over a surface of the substrate.

Abstract: A method for depositing a semiconductor structure on a surface of a substrate is disclosed. The method may include: depositing a first group IVA semiconductor layer over a surface of the substrate; contacting an exposed surface of the first group IVA semiconductor layer with a first gas comprising a first chloride gas; and depositing a second group IVA semiconductor layer over a surface of the first group IVA semiconductor layer. Related semiconductor structures are also disclosed.

Abstract: Methods for depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber are provided. The method may include: heating the substrate to a deposition temperature of less than 550° C.; simultaneously contacting the substrate with a silicon precursor, a n-type dopant precursor, and a p-type dopant precursor; and depositing the co-doped polysilicon film on the surface of the substrate. Related semiconductor structures are also disclosed.