Abstract: A door assembly of a motor vehicle door, having an inner door part with a lateral frame portion and a door module as well as a wiring harness pre-mounted thereon, wherein on the lateral frame part a recess is provided into which the wiring harness lies or can be inserted.

Abstract: A device for a frameless vehicle door includes a counter bearing, a guide rail mounted thereon for a window regulator, and an adjusting device for inclining the guide rail along an adjusting direction oriented obliquely to the counter bearing. The adjusting device can be actuated by a tool. An access direction of the tool is oriented obliquely to the adjusting direction. The adjusting device has at least two adjusting components that can be moved relative to one another, namely, a threaded bolt oriented along the adjusting direction and at least one threaded nut screwed thereon. One of the adjusting components is fixed to the guide rail or the counter bearing for conjoint rotation, and the other is rotatably mounted. The rotatably mounted adjusting component has a drive contour and can be driven by to axially adjust the adjusting components with respect to one another along the adjusting direction.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for clock recovery in subcarrier based coherent optical systems. In one aspect, an apparatus includes a plurality of phase detectors configured to generate a plurality of phase detection outputs by detecting a plurality of digital signals associated with a plurality of frequency bands, each of the plurality of phase detection outputs being associated with a respective one of the plurality of frequency bands, alignment circuitry coupled to the plurality of phase detectors and configured to align phases of the plurality of phase detection outputs to be substantially same, and averaging circuitry coupled to the alignment circuitry and configured to generate a particular output based on the plurality of phase detection outputs with the aligned phases. The plurality of digital signals is adjusted based on the particular output.

Abstract: A carrier component for a vehicle, e.g. in the form of an assembly or module carrier for a vehicle door is provided. The carrier component comprises a sealing channel at least in a protruding region in which a portion for a functional component protruding beyond the edge of the carrier base surface or for a functional component arranged to protrude from the carrier component extends across the sealing channel in cross-section is formed by at least two legs which each define an outer edge of the sealing channel and whose ends lie in a channel plane which extends inclined relative to a carrier plane defined by the carrier base surface, so that the sealing channel is open in a direction in space defining the carrier plane and a seal also can easily be injection-molded to the carrier component in the protruding region.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for clock recovery in subcarrier based coherent optical systems. In one aspect, an apparatus includes a plurality of phase detectors configured to generate a plurality of phase detection outputs by detecting a plurality of digital signals associated with a plurality of frequency bands, each of the plurality of phase detection outputs being associated with a respective one of the plurality of frequency bands, alignment circuitry coupled to the plurality of phase detectors and configured to align phases of the plurality of phase detection outputs to be substantially same, and averaging circuitry coupled to the alignment circuitry and configured to generate a particular output based on the plurality of phase detection outputs with the aligned phases. The plurality of digital signals is adjusted based on the particular output.

Abstract: A circuit arrangement for an onboard network of a motor vehicle, includes a line having a first inductivity and connecting a component of a power electronics of an onboard network with an element, wherein the component is adapted for being clocked during operation of the power electronics at a clock frequency; and an absorber circuit assigned to the line and having a second inductivity and a capacitance, wherein the second inductivity of the absorber circuit is coupled with the first inductivity of the line.

Abstract: A high speed signal generator comprises a digital signal processing (DSP) block configured to process an input digital signal to generate in parallel a first digital sub-band signal having frequency components within a first spectral range and a second digital sub-band signal having frequency components within the first spectral range. A first Digital-to-Analog Converter (DAC) is configured to process the first digital sub-band signal to generate a first analog sub-band signal and a second DAC is configured to process the second digital sub-band signal to generate a second analog sub-band signal. A combiner is to combine the first analog sub-band signal and the second analog sub-band signal to generate an output analog signal having frequency components covering a substantially continuous spectral range from a lower frequency f1 to a higher frequency f2.

Abstract: A high speed signal generator comprises a digital signal processing (DSP) block configured to process an input digital signal to generate in parallel a first digital sub-band signal having frequency components within a first spectral range and a second digital sub-band signal having frequency components within the first spectral range. A first Digital-to-Analog Converter (DAC) is configured to process the first digital sub-band signal to generate a first analog sub-band signal and a second DAC is configured to process the second digital sub-band signal to generate a second analog sub-band signal. A combiner is to combine the first analog sub-band signal and the second analog sub-band signal to generate an output analog signal having frequency components covering a substantially continuous spectral range from a lower frequency f1 to a higher frequency f2.

Abstract: A circuit arrangement for an onboard network of a motor vehicle, includes a line having a first inductivity and connecting a component of a power electronics of an onboard network with an element, wherein the component is adapted for being clocked during operation of the power electronics at a clock frequency; and an absorber circuit assigned to the line and having a second inductivity and a capacitance, wherein the second inductivity of the absorber circuit is coupled with the first inductivity of the line.

Abstract: A high-speed signal generator. A digital signal processing (DSP) block generates a set of N (where N is an integer and N?2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2. A respective Digital-to-Analog Converter (DAC) processes each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs. A combiner combines the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±NFs/2.

Abstract: A carrier component for a vehicle, e.g. in the form of an assembly or module carrier for a vehicle door is provided. The carrier component comprises a sealing channel at least in a protruding region in which a portion for a functional component protruding beyond the edge of the carrier base surface or for a functional component arranged to protrude from the carrier component extends across the sealing channel in cross-section is formed by at least two legs which each define an outer edge of the sealing channel and whose ends lie in a channel plane which extends inclined relative to a carrier plane defined by the carrier base surface, so that the sealing channel is open in a direction in space defining the carrier plane and a seal also can easily be injection-molded to the carrier component in the protruding region.

Abstract: A high-speed signal generator. A digital signal processing (DSP) block generates a set of N (where N is an integer and N?2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2, where Fs is a sample rate of the digital sub-band signals. A respective Digital-to-Analog Converter (DAC) processes each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs/2. A combiner combines the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±NFs/2.

Abstract: A high-speed signal generator. A digital signal processing (DSP) block generates a set of N (where N is an integer and N?2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2, where Fs is a sample rate of the digital sub-band signals. A respective Digital-to-Analog Converter (DAC) processes each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs/2. A combiner combines the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±NFs/2.

Abstract: A high-speed signal generator. A digital signal processing (DSP) block generates a set of N (where N is an integer and N?2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2, where Fs is a sample rate of the digital sub-band signals. A respective Digital-to-Analog Converter (DAC) processes each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs/2. A combiner combines the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±NFs/2.

Abstract: A grinding assembly contacts a tire supported by a frame relative to the tire. The grinding assembly includes at least one section, and an axial positioning assembly supporting the at least one section. The axial positioning assembly enables the at least one section to be axially repositioned relative to the tire. The at least one section includes a grinding head, where the grinding head includes a grindstone rotatably supported thereon, the grindstone having rounded shoulders at its axial extremities. The grinding assembly further includes a radial positioning assembly supporting the grinding head for radial movement with respect to the tire.

Abstract: Providing a dynamic data translation service in a framework that encapsulates other valuable service functions is disclosed. An information technology infrastructure operates in different environments, uses different formats and accesses complex and frequently changing data schemas. The service provider framework provides core computing process automation and dynamic data translation functionality in an encapsulated service that shields requesting systems from data schemas that are often both complex and prone to frequent changes.

Abstract: A grinding assembly contacts a tire supported by a frame relative to the tire. The grinding assembly includes at least one section, and an axial positioning assembly supporting the at least one section. The axial positioning assembly enables the at least one section to be axially repositioned relative to the tire. The at least one section includes a grinding head, where the grinding head includes a grindstone rotatably supported thereon, the grindstone having rounded shoulders at its axial extremities. The grinding assembly further includes a radial positioning assembly supporting the grinding head for radial movement with respect to the tire.

Abstract: A circuit (10) to acquire a more-preferred stored SID element (62) includes memory (20) and logic circuitry (30). The memory (20) stores a roaming list (60), such as a PRL, that includes a plurality of SID elements ranked according to an order of preference including at least one more-preferred stored SID element (62) and at least one less-preferred stored SID element (64). The logic circuitry (30) is coupled to the memory (20) and performs a first more-preferred SID acquisition sequence (80) and then second more-preferred SID acquisition sequence (82). The second more-preferred SID acquisition sequence (82) includes repeatedly attempting acquisition of the at least one more-preferred stored SID element (62) during the second more-preferred SID acquisition sequence (82) while also attempting to acquire the at least one less-preferred SID element (64) if desired.

Abstract: A grinding assembly contacts a tire supported by a frame relative to the tire. The grinding assembly includes at least one section, and an axial positioning assembly supporting the at least one section. The axial positioning assembly enables the at least one section to be axially repositioned relative to the tire. The at least one section includes a grinding head, where the grinding head includes a grindstone rotatably supported thereon, the grindstone having rounded shoulders at its axial extremities. The grinding assembly further includes a radial positioning assembly supporting the grinding head for radial movement with respect to the tire.

Abstract: A high-speed signal generator. A digital signal processing (DSP) block generates a set of N (where N is an integer and N?2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2, where Fs is a sample rate of the digital sub-band signals. A respective Digital-to-Analog Converter (DAC) processes each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs/2. A combiner combines the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±NFs/2.