Abstract: A method for providing accurate temperature sensing of a substrate utilizing the PN junction of a transistor formed on the substrate is described.

Abstract: A fusible link between metallization layers of a semiconductor device comprises a tungsten plug deposited in a via interconnecting two aluminum metallization layers.

Abstract: In accordance with the principles of the invention, an integrated circuit comprises a substrate having a first FET formed on the substrate. The first FET has a first terminal coupleable to a load, a second terminal and a control terminal. The second terminal is connected to the substrate. The substrate comprises a parasitic body diode coupled between the first terminal and the substrate. The body diode is disposed such that it becomes conductive when a reverse voltage across the FET first terminal and the substrate is at least a first diode forward voltage. A voltage detector is formed on the substrate. The voltage detector has a first input coupled to the FET first terminal, a second input coupled to the substrate, and an output coupled to the FET control terminal. The voltage detector is responsive to a reverse voltage level at the FET first terminal that is less than the first diode forward voltage to turn the FET on for the duration of a reverse voltage having at least said reverse voltage level.

Abstract: A method for providing accurate temperature sensing of a substrate utilizing the PN junction of a transistor formed on the substrate is described.

Abstract: A method for providing accurate temperature sensing of a substrate utilizing the PN junction of a transistor formed on the substrate is described.

Abstract: In accordance with the principles of the invention, an integrated circuit comprises a substrate having a first FET formed on the substrate. The first FET has a first terminal coupleable to a load, a second terminal and a control terminal. The second terminal is connected to the substrate. The substrate comprises a parasitic body diode coupled between the first terminal and the substrate. The body diode is disposed such that it becomes conductive when a reverse voltage across the FET first terminal and the substrate is at least a first diode forward voltage. A voltage detector is formed on the substrate. The voltage detector has a first input coupled to the FET first terminal, a second input coupled to the substrate, and an output coupled to the FET control terminal. The voltage detector is responsive to a reverse voltage level at the FET first terminal that is less than the first diode forward voltage to turn the FET on for the duration of a reverse voltage having at least said reverse voltage level.

Abstract: A method for providing accurate temperature sensing of a substrate utilizing the PN junction of a transistor formed on the substrate is described.

Abstract: An integrated circuit comprising a series pass transistor for sourcing current from the positive side of a battery to an inductive load includes integrated circuitry for providing a direct current conduction path between ground and the inductive load as the series pass transistor is turned off by the battery being disconnected therefrom during normal operation so that the stored inductive energy of the inductive load is dissipated. The integrated circuitry includes a silicon controlled rectifier (SCR) coupled between the output of the integrated circuit and ground as well as a Zener diode coupled between the gate and anode of the SCR.

Abstract: A compensation circuit for stabilization of a circuit node coupled to an integrated circuit substrate by a parasitic capacitance of a value C.sub.1 has a displacement current substantially equal to C.sub.1 dv/dt. A switching device having a gain beta can either supply a current to, or draw a current from, the circuit node substantially equal to C.sub.2 .beta. dv/dt which is greater than the displacement current thereby obviating oscillation of an integrated circuit output due to capacitive coupling of the substrate to sensitive circuit nodes.

Abstract: A method is disclosed for eliminating latch-up and analog signal errors in power circuits having a vertical output transistor structure wherein a P-type chip substrate serves as a collector of a saturating vertical PNP transistor. When the P-type substrate rises to V.sub.CC, current is injected into N-type epitaxial layer regions which may then be collected by P-type regions diffused in the epitaxial regions. Circuit problems due to these parasitic currents are avoided by providing dominantly negative feedback for potential latch mechanisms triggered by the injected currents, and providing balancing means to cancel the effects of the injected currents in analog signal paths.

Abstract: An integrated circuit and method for biasing an impurity region, in particular an epitaxial layer, to a level substantially equal to a supply voltage level yet exhibiting a high reverse breakdown voltage to negative transients of the supply voltage. The integrated circuit and method is of especial utility in power BIMOS and other applications having the substrate at or near the supply voltage level.

Abstract: A thermal shut-down circuit is provided that is monolithically integrated in a power BIMOS process wherein a vertical power PNP output transistor comprises a P-type substrate as a collector. The circuit compensates for vertical currents injected from the P-substrate into lateral transistors. A first PNP transistor has an emitter connected to a first resistor and conducts a first current. A second PNP transistor has an emitter connected to a second resistor and conducts a second current. A third resistor has one terminal coupled to the emitter of the second transistor. A fourth resistor is coupled in series with an output means, the combination thereof being coupled in parallel with the second and third resistors.

Abstract: Circuitry is provided for current limiting the output current of a power substrate PNP transistor comprised of a plurality of emitters (e.g. 260). A resistor is placed between a fraction of the plurality of emitters (e.g. 8) and a source of supply voltage. When the power device is turned on, the current is drawn through the resistor causing a voltage drop thereacross. This voltage drop is monitored and when it reaches a certain level, a control signal is generated which ultimately results in limiting the conducted current of the power transistor.

Abstract: The self-protecting load driver circuit includes an output transistor having an emitter coupled to a current sensor and a collector adapted to be coupled to the electrical load. A comparator senses the magnitude of a current sensor signal and applies trigger signals to a time delay circuit which is connected between the output of the comparator and the control terminal of a control circuit for the protected transistor. The rise time of the voltage across the current sensor depends on the inductance, for instance, of the load. The time delay circuit enables the control circuit to disable the output transistor for a predetermined time duration in response to the threshold voltage of the comparator being exceeded by the sensor voltage. At other times, the protected transistor is saturated by the control circuit so that power is delivered to the load.

Abstract: An amplifier circuit is disclosed which utilizes a differential-to-single ended converter having a floating current mirror. The amplifier includes a differential driving circuit having first and second differential output terminals which are respectively connected to first and second current supplies and an output transistor. The current mirror includes a diode-connected transistor having a base-to-emitter junction connected in parallel with the base-to-emitter junction of a further transistor. The base electrode of the diode-connected transistor is connected to one of the differential output terminals and the collector electrode of the further transistor is connected to the other differential output terminal.

Abstract: A two transistor voltage reference circuit controls the ratio of the current densities of two transistors by a negative feedback loop. A voltage corresponding to the difference in the base-to-emitter voltages of the two transistors is developed which has a positive temperature coefficient (TC) and which is connected in series with the base-to-emitter voltage of one of the two transistors having a negative TC. The circuit parameters are selected so that the resultant combined voltage has a predetermined, composite TC. A zener diode is included in the negative feedback loop and arranged to have a TC which cancels the predetermined composite TC to develop a reference voltage having a high magnitude that has minimal variation with temperature change.

Abstract: A current supply circuit is disclosed having a field effect transistor and negative feedback for degenerating the magnitude of the current supplied thereby. The negative feedback can be provided by a diffused resistor connected between the gate and source electrodes of the current supply field effect transistor. A differential amplifier which includes a pair of differentially coupled amplifying field effect transistors is coupled to the current supply circuit. The negative feedback enables the current supply device to provide a current which compensates the differentially coupled field effect transistors over processing while not deleteriously affecting the temperature characteristics thereof. A bipolar diode and a bipolar transistor can be included in the current supply for enabling the resistor to take up less chip area and for allowing more flexibility in the design of the geometry of the current supply, field effect transistor.

Abstract: A clamp circuit is disclosed which includes a transistor connected between the multiple collectors of a bias current device for complementary output transistors and the output terminal of a driver circuit. The clamp transistor is rendered conductive by signals at the output terminal of the driver circuit which would otherwise heavily saturate the bias current device. The clamp transistor conducts current to provide additional needed bias to the complementary output device and to keep such current from disturbing the magnitudes of currents provided by a current generator circuit which is also connected to the bias current device.

Abstract: An amplifier circuit is disclosed which includes a current supply circuit having a field effect transistor and negative feedback for degenerating the magnitude of the current supplied thereby. The negative feedback can be provided by a diffused resistor connected between the gate and source electrodes of the current supply field effect transistor. A differential amplifier which includes a pair of differentially coupled amplifying field effect transistors is coupled to the current supply circuit. The negative feedback enables the current supply device to provide a current which compensates the differentially coupled field effect transistors over processing while not deleteriously affecting the temperature characteristics thereof. A bipolar diode and a bipolar transistor can be included in the current supply for enabling the resistor to take up less chip area and for allowing more flexibility in the design of the geometry of the current supply, field effect transistor.

Abstract: A common emitter amplifier having a resistor in series with its emitter and a resistor in series with its collector is temperature stabilized by providing a current source in parallel with the resistor in series with the collector. The current source provides additional emitter current to the transistor to decrease the transistors internal AC emitter resistance. Cascoded transistors are also used to improve the performance of the amplifier.