Patents by Inventor David L. O'Meara

David L. O'Meara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087892
    Abstract: A method of forming a semiconductor device includes forming, over a hardmask layer and an underlying layer of a substrate, a pattern of first trenches between adjacent template lines, each of the first trenches exposing a portion of the hardmask layer, and each of the template lines including a mandrel and spacers on sidewalls of the mandrel; forming a pattern of first blocks over the pattern of the first trenches and the template lines, the first blocks dividing the first trenches to form a pattern of first stencil trenches; transferring the pattern of first stencil trenches to the hardmask layer to form a pattern of first hardmask trenches, each of the first hardmask trenches exposing a portion of the underlying layer; forming a first fill layer filling the first hardmask trenches and exposing the mandrels; selectively removing the mandrels to form second trenches, each of the second trenches exposing a portion of the hardmask layer; and forming a conformal liner in the second trenches and over a surface of
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Eric Chih-Fang Liu, Katie Lutker-Lee, Steven Grzeskowiak, Jodi Grzeskowiak, Jeffrey Smith, David L. O'Meara
  • Patent number: 11567407
    Abstract: A method of processing a substrate includes: providing structures on a surface of a substrate; depositing a self-assembled monolayer (SAM) over the structures and the substrate, the SAM being reactive to a predetermined wavelength of radiation; determining a first pattern of radiation exposure, the first pattern of radiation exposure having a spatially variable radiation intensity across the surface of the substrate and the structures; exposing the SAM to radiation according to the first pattern of radiation exposure, the SAM being configured to react with the radiation; developing the SAM with a predetermined removal fluid to remove portions of the SAM that are not protected from the predetermined fluid; and depositing a spacer material on the substrate and the structures, the spacer material being deposited at varying thicknesses based on an amount of the SAM remaining on the surface of the substrate and the structures.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 31, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Richard Farrell, Hoyoung Kang, David L. O'Meara
  • Patent number: 11532517
    Abstract: In one embodiment, a method includes providing a substrate comprising a source/drain contact region and a dummy gate, forming a first etch stop layer aligned to the source/drain contact region, where the first etch stop layer does not cover the dummy gate. The method may include forming a second etch stop layer over the first etch stop layer, the second etch stop layer covering the first etch stop layer and the dummy gate. The method may include converting the dummy gate to a metal gate. The method may include removing the second etch stop layer using a plasma etching process. The method may include removing the first etch stop layer.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: December 20, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Yun Han, Andrew Metz, Xinghua Sun, David L. O'Meara, Kandabara Tapily, Henan Zhang, Shan Hu
  • Publication number: 20220344169
    Abstract: A method includes providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate with a dielectric spacer separating each source/drain contact region from adjacent metal gate stacks. Each source/drain region is recessed within an opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the recess and dielectric spacers provide sidewalls. The etch stop layer is formed on the substrate such that it conformally covers the metal gate stacks, the sidewalls and the bottom of each recess, and a sacrificial layer is formed over each of the metal gate stacks and on at least a portion of each sidewall. The etch stop layer is removed from the bottom of each recess to expose the source/drain contact, and the sacrificial layer is then removed from the metal gate stacks and the sidewalls of each recess.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 27, 2022
    Applicant: Tokyo Electron Limited
    Inventors: Yun HAN, David L. O'MEARA, Cheryl ALIX, Andrew METZ, Shan HU, Henan ZHANG
  • Patent number: 11417526
    Abstract: A method of forming a device includes depositing a first etch mask layer over a mandrel formed using a lithography process. The method includes depositing a second etch mask layer over the first etch mask layer. The method includes, using a first anisotropic etching process, etching the first etch mask layer and the second etch mask layer to form an etch mask including the first etch mask layer and the second etch mask layer. The method includes removing the mandrel to expose an underlying surface of the layer to be patterned. The method includes, using the etch mask, forming a feature by performing a second anisotropic etching process to pattern the layer to be patterned, where during the first anisotropic etching process, the first etch mask layer etches at a first rate and the second etch mask layer etches at a second rate, and where the first rate is different from the second rate.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: August 16, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David L. O'Meara, Eric Chih-Fang Liu, Jodi Grzeskowiak, Anton deVilliers, Akiteru Ko, Anthony Dip
  • Publication number: 20220139776
    Abstract: A method for filling recessed features with a low-resistivity metal includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, and depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature. The method further includes removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature, where the removing includes exposing the patterned substrate to an etching gas containing ozone.
    Type: Application
    Filed: October 21, 2021
    Publication date: May 5, 2022
    Inventors: Kai-Hung Yu, David L. O'Meara, Hisashi Higuchi, Hirokazu Aizawa, Omid Zandi, Cory Wajda, Gerrit J. Leusink
  • Publication number: 20210242089
    Abstract: In one embodiment, a method includes providing a substrate comprising a source/drain contact region and a dummy gate, forming a first etch stop layer aligned to the source/drain contact region, where the first etch stop layer does not cover the dummy gate. The method may include forming a second etch stop layer over the first etch stop layer, the second etch stop layer covering the first etch stop layer and the dummy gate. The method may include converting the dummy gate to a metal gate. The method may include removing the second etch stop layer using a plasma etching process. The method may include removing the first etch stop layer.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Inventors: Yun Han, Andrew Metz, Xinghua Sun, David L. O'Meara, Kandabara Tapily, Henan Zhang, Shan Hu
  • Publication number: 20210242020
    Abstract: A method of forming a device includes depositing a first etch mask layer over a mandrel formed using a lithography process. The method includes depositing a second etch mask layer over the first etch mask layer. The method includes, using a first anisotropic etching process, etching the first etch mask layer and the second etch mask layer to form an etch mask including the first etch mask layer and the second etch mask layer. The method includes removing the mandrel to expose an underlying surface of the layer to be patterned. The method includes, using the etch mask, forming a feature by performing a second anisotropic etching process to pattern the layer to be patterned, where during the first anisotropic etching process, the first etch mask layer etches at a first rate and the second etch mask layer etches at a second rate, and where the first rate is different from the second rate.
    Type: Application
    Filed: February 3, 2020
    Publication date: August 5, 2021
    Inventors: David L. O'Meara, Eric Chih-Fang Liu, Jodi Grzeskowiak, Anton deVilliers, Akiteru Ko, Anthony Dip
  • Patent number: 10734228
    Abstract: Embodiments are disclosed for processing microelectronic workpieces to apply stress engineering to self-aligned multi-patterning (SAMP) processes. The disclosed processing methods utilize stress in a substrate in a SAMP process to improve resulting pattern parameters. Initially, a high stress film is deposited on the frontside and the backside of the substrate, and the high stress film provides biaxial stress to the substrate due to the deposition process for the high stress film. Next, a SAMP process is performed to form spacers in a spacer pattern. This spacer pattern is then transferred to underlying layers to form a patterned structure. The high stress film provides axial stress in at least one direction along a portion of the patterned structure during the pattern transfer thereby improving resulting pattern formation.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: August 4, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Eric Chih-Fang Liu, Akiteru Ko, David L. O'Meara
  • Patent number: 10700009
    Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 30, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Nicholas Joy, Eric Chih Fang Liu, David L. O'Meara, David Rosenthal, Masanobu Igeta, Cory Wajda, Gerrit J. Leusink
  • Publication number: 20200103755
    Abstract: A method of processing a substrate includes: providing structures on a surface of a substrate; depositing a self-assembled monolayer (SAM) over the structures and the substrate, the SAM being reactive to a predetermined wavelength of radiation; determining a first pattern of radiation exposure, the first pattern of radiation exposure having a spatially variable radiation intensity across the surface of the substrate and the structures; exposing the SAM to radiation according to the first pattern of radiation exposure, the SAM being configured to react with the radiation; developing the SAM with a predetermined removal fluid to remove portions of the SAM that are not protected from the predetermined fluid; and depositing a spacer material on the substrate and the structures, the spacer material being deposited at varying thicknesses based on an amount of the SAM remaining on the surface of the substrate and the structures.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 2, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Richard FARRELL, Hoyoung KANG, David L. O'MEARA
  • Patent number: 10580650
    Abstract: Embodiments of the invention provide a substrate processing method for bottom-up formation of a film in a recessed feature. According to one embodiment, the method includes providing a substrate containing a first layer and a second layer on the first layer, the second layer having a recessed feature extending through the second layer, and depositing a non-conformal mask layer on the substrate, where the mask layer has an overhang at an opening of the recessed feature. The method further includes removing the mask layer from a bottom of the recessed feature, while maintaining at least a portion of the overhang at the opening, selectively depositing a film on the bottom of the recessed feature, and removing the mask layer overhang from the substrate. The processing steps may be repeated at least once until the film has a desired thickness in the recessed feature.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 3, 2020
    Assignee: Tokyo Electron Limited
    Inventors: David L. O'Meara, Kandabara N. Tapily, Nihar Mohanty
  • Publication number: 20190189445
    Abstract: Embodiments are disclosed for processing microelectronic workpieces to apply stress engineering to self-aligned multi-patterning (SAMP) processes. The disclosed processing methods utilize stress in a substrate in a SAMP process to improve resulting pattern parameters. Initially, a high stress film is deposited on the frontside and the backside of the substrate, and the high stress film provides biaxial stress to the substrate due to the deposition process for the high stress film. Next, a SAMP process is performed to form spacers in a spacer pattern. This spacer pattern is then transferred to underlying layers to form a patterned structure. The high stress film provides axial stress in at least one direction along a portion of the patterned structure during the pattern transfer thereby improving resulting pattern formation.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 20, 2019
    Inventors: Eric Chih-Fang Liu, Akiteru Ko, David L. O'Meara
  • Publication number: 20190103363
    Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Inventors: Kai-Hung Yu, Nicholas Joy, Eric Chih Fang Liu, David L. O'Meara, David Rosenthal, Masanobu Igeta, Cory Wajda, Gerrit J. Leusink
  • Patent number: 10079151
    Abstract: Embodiments of the invention provide a processing method for bottom-up deposition of a film in a recessed feature. According to one embodiment, the method includes a) providing a substrate containing a recessed feature having a bottom and a sidewall, b) depositing a film on the bottom and on the sidewall of the recessed feature, and c) covering the film at the bottom of the recessed feature with a mask layer. The method further includes d) etching the film from the sidewall, and e) removing the mask layer to expose the film at the bottom of the recessed feature. Steps b)-e) may be repeated at least once until the film at the bottom of the recessed feature has a desired thickness. In one example, the recessed feature may be filled with the film.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: September 18, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N Tapily, David L O'Meara, Kaushik A Kumar
  • Patent number: 9899224
    Abstract: A method is provided for forming an ultra-shallow boron doping region in a semiconductor device. The method includes depositing a diffusion filter layer on a substrate, the diffusion filter containing a boron nitride layer, a boron oxynitride layer, a silicon nitride layer, or a silicon oxynitride layer, and depositing a boron dopant layer on the diffusion filter layer, the boron dopant layer containing boron oxide, boron oxynitride, or a combination thereof, with the proviso that the diffusion filter layer and the boron dopant layer do not contain the same material. The method further includes heat-treating the substrate to form the ultra-shallow boron dopant region in the substrate by controlled diffusion of boron from the boron dopant layer through the diffusion filter layer and into the substrate.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 20, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Steven P. Consiglio, Robert D. Clark, David L. O'Meara
  • Patent number: 9831099
    Abstract: Embodiments of the invention describe a method and apparatus for multi-film deposition and etching in a batch processing system. According to one embodiment, the method includes arranging the substrates on a plurality of substrate supports in a process chamber, where the process chamber contains processing spaces defined around an axis of rotation in the process chamber, rotating the plurality of substrate supports about the axis of rotation, depositing a first film on a patterned film on each of the substrates by atomic layer deposition, and etching a portion of the first film on each of the substrates, where etching a portion of the first film includes removing at least one horizontal portion of the first film while substantially leaving vertical portions of the first film. The method further includes repeating the depositing and etching steps for a second film that contains a different material than the first film.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: November 28, 2017
    Assignee: Tokyo Electron Limited
    Inventors: David L. O'Meara, Anthony Dip
  • Publication number: 20170294312
    Abstract: Embodiments of the invention provide a substrate processing method for bottom-up formation of a film in a recessed feature. According to one embodiment, the method includes providing a substrate containing a first layer and a second layer on the first layer, the second layer having a recessed feature extending through the second layer, and depositing a non-conformal mask layer on the substrate, where the mask layer has an overhang at an opening of the recessed feature. The method further includes removing the mask layer from a bottom of the recessed feature, while maintaining at least a portion of the overhang at the opening, selectively depositing a film on the bottom of the recessed feature, and removing the mask layer overhang from the substrate. The processing steps may be repeated at least once until the film has a desired thickness in the recessed feature.
    Type: Application
    Filed: April 11, 2017
    Publication date: October 12, 2017
    Inventors: David L. O'Meara, Kandabara N. Tapily, Nihar Mohanty
  • Publication number: 20170236719
    Abstract: Embodiments of the invention describe a method and apparatus for multi-film deposition and etching in a batch processing system. According to one embodiment, the method includes arranging the substrates on a plurality of substrate supports in a process chamber, where the process chamber contains processing spaces defined around an axis of rotation in the process chamber, rotating the plurality of substrate supports about the axis of rotation, depositing a first film on a patterned film on each of the substrates by atomic layer deposition, and etching a portion of the first film on each of the substrates, where etching a portion of the first film includes removing at least one horizontal portion of the first film while substantially leaving vertical portions of the first film. The method further includes repeating the depositing and etching steps for a second film that contains a different material than the first film.
    Type: Application
    Filed: February 9, 2017
    Publication date: August 17, 2017
    Inventors: David L. O'Meara, Anthony Dip
  • Publication number: 20170092508
    Abstract: Embodiments of the invention provide a processing method for bottom-up deposition of a film in a recessed feature. According to one embodiment, the method includes a) providing a substrate containing a recessed feature having a bottom and a sidewall, b) depositing a film on the bottom and on the sidewall of the recessed feature, and c) covering the film at the bottom of the recessed feature with a mask layer. The method further includes d) etching the film from the sidewall, and e) removing the mask layer to expose the film at the bottom of the recessed feature. Steps b)-e) may be repeated at least once until the film at the bottom of the recessed feature has a desired thickness. In one example, the recessed feature may be filled with the film.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 30, 2017
    Inventors: Kandabara N. Tapily, David L. O'Meara, Kaushik A. Kumar