Abstract: Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.

Abstract: A antireflective film 50 is formed on a thermocouple 42 arranged in a processing vessel 1 of a heat treatment apparatus in order to improve the transient response characteristics of the thermocouple 42. In a typical embodiment, the thermocouple 42 is made by connecting a platinum wire 43A and a platinum-rhodium alloy wire 43B, and the antireflective film 50 is composed by stacking a silicon nitride layer 50C, silicon layer 50B and a silicon nitride layer 50A in that order.

Abstract: A method is provided for forming a microstructure with an interfacial oxide layer by using a diffusion filter layer to control the oxidation properties of a substrate associated with formation of a high-k layer into the microstructure. The diffusion filter layer controls the oxidation of the surface. The interfacial oxide layer can be formed during an oxidation process that is carried out following deposition of a high-k layer onto the diffusion filter layer, or during deposition of a high-k layer onto the diffusion filter layer.

Abstract: A antireflective film 50 is formed on a thermocouple 42 arranged in a processing vessel 1 of a heat treatment apparatus in order to improve the transient response characteristics of the thermocouple 42. In a typical embodiment, the thermocouple 42 is made by connecting a platinum wire 43A and a platinum-rhodium alloy wire 43B, and the antireflective film 50 is composed by stacking a silicon nitride layer 50C, silicon layer 50B and a silicon nitride layer 50A in that order.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: A semiconductor device has a semiconductor region that functions as a channel between two metal conductors. In the semiconductor region and adjacent to the metal conductors are doped regions of an opposite conductivity type to that of the channel that are source and drain regions, which are electrically coupled laterally to the two metal conductors and function as ohmic contacts. The semiconductor region is epitaxially grown through a hole in an insulating layer that underlies the two metal conductors. Under the insulating layer is a semiconductor layer that forms the seed for epitaxially growing the semiconductor layer. The hole is also formed through another relatively thick insulating layer over the two metal conductors.

Abstract: In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.

Abstract: A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). The growth of the nanoclusters (19) may be accomplished using low pressure chemical vapor deposition (LPCVD) or ultra high vacuum chemical vapor deposition (UHCVD) processes. Such growth may be facilitated by formation of a nitrogen-containing layer (502) overlying the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20).

Abstract: A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).

Abstract: A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: A low temperature chemical vapor deposition process comprising heating in a chemical vapor depositon reactor a substrate upon which deposition is desired to a temperature of from about 550.degree. C. to about 750.degree. C. in a chemical vapor deposition reactor having a pressure of from about 0.1 torr to approximately atmospheric pressure, introducing into the reactor a silicon-containing feed and optionally an oxygen containing feed, said silicon containing feed consisting essentially of one or more compounds having the general formula ##STR1## wherein: R.sub.1, R.sub.2, R.sub.3 and R.sub.4 are hydrogen, azido or C-2 to C-6 alkyl, aryl or C-7 to C-10 aralkyl groups, at least one but not more than three of R.sub.1, R.sub.2, R.sub.3 and R.sub.4, being azido, and maintaining the temperature and pressure to cause a film of silicon nitride, silicon oxynitride or silicon dioxide to deposit is disclosed.

Abstract: A low temperature chemical vapor deposition process comprising heating a substrate upon which deposition is desired to a temperature of from about 350.degree. C. to about 700.degree. C. in a chemical vapor deposition reactor at a pressure of from about 0.1 torr to atmospheric pressure, introducing into the reactor a silicon-containing feed and an oxygen containing feed, said silicon containing feed consisting essentially of one or more compounds having the general formula ##STR1## wherein: R.sub.1, R.sub.2, and R.sub.3 are hydrogen, azido or 1-6 carbon alkyl, phenyl or 7 to 10 carbon alkaryl groups, at least one of R.sub.1 and R.sub.2 being 1-6 carbon alkyl, phenyl or 7-10 carbon alkaryl and maintaining the temperature and pressure in said ranges to cause a film of silicon dioxide or silicon oxynitride to deposit on said substrate is disclosed.

Abstract: A method of producing a silicon nitride film on the surface of a substrate by thermal decomposition at said surface of a compound of the class ##STR1## wherein R.sub.1 R.sub.2 and R.sub.3 are hydrogen azido, 1 to 6 carbon alkyl, phenyl, or 7 to 10 carbon alkaryl, at least one of R.sub.1, R.sub.2, and R.sub.3 being 1-6 carbon alkyl, phenyl, or 7 to 10 carbon alkaryl, ethyltriazidosilane being uniquely superior, is disclosed.

Abstract: A chemical vapor deposition process for depositing silicon dioxide comprising the steps of heating a substrate upon which deposition is desired to a temperature of from about 325.degree. C. to about 700.degree. C. in a vacuum having a pressure of from about 0.1 to about 1.5 torr, and introducing a silane selected from the group consisting of alkylsilane, arylsilane and araylkylsilane wherein the alkyl-, aryl- or aralkyl- moiety comprises from 2-6 carbons, and oxygen or carbon dioxide into the vacuum.