Abstract: The present description concerns a converter comprising: a circuit (C1) supplying a first pulse (P1) determined by an interval between an active edge of a first signal (S1) and an active edge of a second signal (S2); a circuit (INT) which, at each first pulse (P1), integrates the first pulse (P1), a second pulse (P2) starting after the first pulse (P1) in synchronism with a clock signal (clk), and a third pulse (P3) starting after the third pulse (P3) in synchronism with the clock signal (clk); a circuit (C3) sampling over one bit (OUT1) an output signal (RES1) of the integrator circuit (INT) at the beginning of each third pulse (P3); and two circuits (C2, C4) generating, for each first pulse (P1), respectively the corresponding second pulse and the third corresponding pulse based on the first bit (OUT1).

Abstract: The present description concerns a converter comprising: a circuit (C1) supplying a first pulse (P1) determined by an interval between an active edge of a first signal (S1) and an active edge of a second signal (S2); a circuit (INT) which, at each first pulse (P1), integrates the first pulse (P1), a second pulse (P2) starting after the first pulse (P1) in synchronism with a clock signal (clk), and a third pulse (P3) starting after the third pulse (P3) in synchronism with the clock signal (clk); a circuit (C3) sampling over one bit (OUT1) an output signal (RES1) of the integrator circuit (INT) at the beginning of each third pulse (P3); and two circuits (C2, C4) generating, for each first pulse (P1), respectively the corresponding second pulse and the third corresponding pulse based on the first bit (OUT1).

Abstract: Radar measuring device including: a first generator of a first periodic radar signal whose frequency varies linearly, over at least one portion Tramp of a period Tin, in a frequency band B; a transmit antenna coupled to an output of the first generator and configured to transmit the first radar signal; a second generator of a second periodic radar signal whose frequency varies linearly, over said portion Tramp of the period Tin, in the frequency band B, which is generated with the same start-up phase as the first radar signal and having, relative to the first radar signal, a configurable delay ?mix; a receive antenna configured to receive at least one echo of the first radar signal; a mixer comprising a first input coupled to the receive antenna and a second input coupled to an output of the second generator.

Abstract: The present disclosure relates to a polar phase or frequency modulator comprising: a normalized delay circuit (602) configured to delay edges of an input carrier signal (CLK_IN) based on normalized delay control values (?i) to generate a modulated output signal (RF_OUT); and a normalized delay calculator (604) configured to receive the modulated output signal (RF_OUT) and to generate the normalized delay control values (?i).

Abstract: A frequency synthesis device includes a servo circuit for controlling an output frequency to an input reference frequency. The circuit includes a first phase accumulator clocked by the reference frequency, a phase comparison block, a loop filter and an oscillator. It further includes a feedback loop connecting the output to the comparison block, having a second phase accumulator clocked by the output frequency. The comparison block includes T phase comparators with logic gates receiving respectively T first logic signals from the servo circuit on T first inputs and T second logic signals from the feedback loop on T second inputs, the T first and second signals having logic levels that continuously depend on values provided by the first and second accumulators according to at least one multi-phase correspondence matrix.

Abstract: The present disclosure relates to a polar phase or frequency modulator comprising: a normalized delay circuit (602) configured to delay edges of an input carrier signal (CLK_IN) based on normalized delay control values (?i) to generate a modulated output signal (RF_OUT); and a normalized delay calculator (604) configured to receive the modulated output signal (RF_OUT) and to generate the normalized delay control values (?i).

Abstract: A frequency synthesis device includes a servo circuit for controlling an output frequency to an input reference frequency. The circuit includes a first phase accumulator clocked by the reference frequency, a phase comparison block, a loop filter and an oscillator. It further includes a feedback loop connecting the output to the comparison block, having a second phase accumulator clocked by the output frequency. The comparison block includes T phase comparators with logic gates receiving respectively T first logic signals from the servo circuit on T first inputs and T second logic signals from the feedback loop on T second inputs, the T first and second signals having logic levels that continuously depend on values provided by the first and second accumulators according to at least one multi-phase correspondence matrix.

Abstract: A device for quantizing an analog input signal, for supply of a continuous-time output signal quantized using a plurality of bits, includes a sign analysis electronic circuit, configured to supply a first signal representative of a first sign bit of the output signal, and an envelope analysis electronic circuit, including a comparator/quantizer with two inputs one of which receives the analog input signal, configured to supply a second signal representative of at least a second bit of the output signal, as a quantized envelope signal, and a feedback loop with continuous-time digital-to-analog conversion of the quantized envelope signal, arranged between the output and the other of the two inputs of the comparator/quantizer. The quantized envelope signal is a signal of which a low pass filtering is representative of the amplitude of an envelope signal of the input signal and the feedback loop includes a low pass filter.

Abstract: This frequency synthesis device comprises a servo circuit for the control of a frequency provided as output by a reference frequency received as input, with this circuit comprising a first phase accumulator clocked at a frequency linked to the reference frequency, a first digital-to-analog converter, a phase comparator, a loop filter and a controlled frequency oscillator providing an electrical signal oscillating at the output frequency. It further comprises a feedback loop connecting the output to the phase comparator, comprising a second phase accumulator clocked at a frequency linked to the output frequency and a second digital-to-analog converter. A reduction in dynamics by quantization is provided between each phase accumulator and each respective digital-to-analog converter, with this quantization being carried out by truncation of digital values of accumulated phases at the output of each phase accumulator.

Abstract: A device for quantizing an analog input signal, for supply of a continuous-time output signal quantized using a plurality of bits, includes a sign analysis electronic circuit, configured to supply a first signal representative of a first sign bit of the output signal, and an envelope analysis electronic circuit, including a comparator/quantizer with two inputs one of which receives the analog input signal, configured to supply a second signal representative of at least a second bit of the output signal, as a quantized envelope signal, and a feedback loop with continuous-time digital-to-analog conversion of the quantized envelope signal, arranged between the output and the other of the two inputs of the comparator/quantizer. The quantized envelope signal is a signal of which a low pass filtering is representative of the amplitude of an envelope signal of the input signal and the feedback loop includes a low pass filter.

Abstract: This frequency synthesis device comprises a servo circuit for the control of a frequency provided as output by a reference frequency received as input, with this circuit comprising a first phase accumulator clocked at a frequency linked to the reference frequency, a first digital-to-analog converter, a phase comparator, a loop filter and a controlled frequency oscillator providing an electrical signal oscillating at the output frequency. It further comprises a feedback loop connecting the output to the phase comparator, comprising a second phase accumulator clocked at a frequency linked to the output frequency and a second digital-to-analog converter. A reduction in dynamics by quantization is provided between each phase accumulator and each respective digital-to-analog converter, with this quantization being carried out by truncation of digital values of accumulated phases at the output of each phase accumulator.

Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.

Abstract: A demodulator including a delay line adapted for receiving an input signal at an input frequency, phase or frequency modulated by symbols with a duration equal to a period of the input signal or very close to that period. The delay line has Nd outputs producing Nd signals at the input frequency but with Nd different delays offset by ?T relative to one another, Nd being an integer number greater than or equal to 1. The demodulator also includes a register of Nd latches each receiving a respective output of the delay line and a clock signal which is the input signal, in order to store the state of the outputs of the delay lines at the end of a period of the clock signal in the register. The content of the register represents a value of an input signal modulation symbol.

Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.

Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.

Abstract: A device for continuous time quantization of an input signal, in order to supply a continuous time output signal that is quantized as two bits, the device including: an electronic circuit, designed to supply a first bit of the output signal called the sign bit which at any time takes a first value when the input signal is positive and a second value when the input signal is negative, and an envelope analysis circuit designed to supply a second bit of the output signal called the envelope variation bit which at any time takes a first value, called high value, when an envelope signal of the input signal is increasing, and a second value, called low value, when the envelope signal is decreasing.

Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.

Abstract: Transmitter device which includes at least: a) one delay line designed to output M signals which are delayed in relation to each other, where M is an integer greater than 1; b) a memory, designed to store at least M digital samples of a waveform, where each digital sample contains N bits, and to output each of the M digital samples successively on N output lines respectively under the control of one of the M delayed signals; and c) a digital-analog converter which includes N inputs linked to N output lines, designed to convert the M digital samples received as input from the N output lines of the memory and to successively output, on an output of the digital-analog converter, each of the M analog converted digital samples which together form an analog signal which is representative of the waveform.

Abstract: A demodulator including a delay line adapted for receiving an input signal at an input frequency, phase or frequency modulated by symbols with a duration equal to a period of the input signal or very close to that period. The delay line has Nd outputs producing Nd signals at the input frequency but with Nd different delays offset by ?T relative to one another, Nd being an integer number greater than or equal to 1. The demodulator also includes a register of Nd latches each receiving a respective output of the delay line and a clock signal which is the input signal, in order to store the state of the outputs of the delay lines at the end of a period of the clock signal in the register . The content of the register represents a value of an input signal modulation symbol.

Abstract: The invention relates to an N-bit asynchronous Quantizer including a 2N?1 signal amplifier stages (G12-G2N?12) arranged in series, the input of the first stage being capable of receiving a signal to be quantized; 2N?1 comparators (C12-C2N?12), one comparator being connected to the output of each amplifier stage (G12-G2N?12), and capable of comparing the value of this output with a predetermined threshold value; and at least 2N?2 delay lines (D12-D2N?12) placed at the output of the 2N?2 first comparators, the signals supplied at the output of the delay lines (D12-D2N?12) and of the last comparator constituting at any instant the quantized binary values of the input signal with a time shift.